DataSheet_SB16C1053APCI_v106
SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
25
8.1.1 Vendor ID
A 16-bit register which represents the manufacturer of the device.
It is a unique ID given by PCI SIG after membership registration. If you do not own a
Vendor ID, it is fine to use 14A1h given to SystemBase by PCI SIG.
8.1.2 Device ID
A 16-bit unique ID of each device given by the Function Manufacturer which can be
assigned by the manufacturer freely. It is related to software driver installation/recognition.
Please refer the Device ID for each mode in Table 8-2.
Table 8–2: Command Register
PORT[2:0]
100
011
000
110
111
001
MODE
1S
1P
2S
2S1P
4S
6S
Device ID
4D01h
4301h
4D02h
4303h
4D04h
4D06h
8.1.3 Command Register
Table 8–3: Command Register
Bit
Type
Description
15:11
RO
Reserved: Hardwired to 00000b
10
RW
Interrupt Disable: This bit controls PCI function’s INTx interrupt signal creation ability. When
it is 0b, function can assert INTx interrupt signal. When it is 1b, function cannot assert INTx
interrupt signal. Default value of this bit is 0b.
9
RO
Hardwired to 0b.
8
RW
SERR Enable: If this bit is set and the function detects a non-fatal error and a fatal error,
error reporting is executed to Root Complex. You can set the kind of errors to report to Device
Control Register. Default value is 0b.
7
RO
Hardwired to 0b.
6
RW
Parity Error Response: A Root Complex Integrated Endpoint that is not associated with a
Root Complex Event Collector is permitted to hardwire this bit to 0b. Default value is 0b.
5
RO
Hardwired to 0b.
4
RO
Hardwired to 0b.
3
RO
Hardwired to 0b.
2
RW
Hardwired to 0b.
1
RW
Memory Address Space Decoder Enable: When this is 0b, Memory Decoder is disabled
and Memory Transactions arriving to this device are responded with Completion of
Unsupported Request state. When it is 1b, Memory Decoder is enabled and memory
transactions arriving to this device are accepted and handled.
0
RW
IO Address Space Decoder Enable: When this is 0b, IO decoder is disabled and IO
transactions arriving to this device are responded with Completion of Unsupported Request
state. When it is 1b, IO decoder is enabled and IO transactions arriving to this device are
accepted and handled.