DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
3
8.1.9 Header Type ............................................................................................................... 27
8.1.10 BIST(Built-In Self Test) .............................................................................................. 27
8.1.11 Base Address Registers .............................................................................................. 28
8.2 Power Management Registers of SB16C1053APCI ................................................................... 30
8.2.1 Capability ID (40h) ...................................................................................................... 30
8.2.2 Pointer to Next Capability (41h).................................................................................... 30
8.2.3 Power Management Capabilities (42~43h) .................................................................... 30
8.2.4 Power Management Control/Status Register (44~45h) ................................................... 31
9. Power Management ....................................................................................................................... 32
9.1 PCI Power Management ........................................................................................................ 32
9.1.1 PCI Function Power State ............................................................................................. 32
9.2 SB16C1053APCI Power Management Pins and Functions ......................................................... 33
9.2.1 SB16C1053APCI Pins for Power Management ................................................................ 33
9.2.2 SB16C1053APCI Power Management Wakeup implementation ....................................... 34
9.2.3 3.3Vaux Presence Detection & Power Routing ............................................................... 34
10. Option I/O Space ......................................................................................................................... 35
10.1 General Information Register 0 – Serial Port Number (GIR0, BAR4+0h) .................................. 36
10.2 General Information Register 1 – Product Version (GIR1, BAR4+1h) ...................................... 36
10.3 General Information Register 2 – Parallel Port Number (GIR2, BAR4+2h) ............................... 36
10.4 General Information Register 3 – Core Version (GIR3, BAR4+3h) ........................................... 36
10.5 Software Reset Register (SRR, BAR4+3h) ............................................................................. 36
10.6 Device Information Register (DIR, BAR4+4h) ....................................................................... 36
10.7 Interface Information Register 0, 1 (IIR0, BAR4+8h/ IIR1, BAR4+9h) .................................... 37
10.8 Interrupt Mask Register (IMR, BAR4+Ch) ............................................................................. 39
10.9 Interrupt Poll Register (IPR, BAR4+10h) ............................................................................... 40
10.10 Parallel Port FIFO TX Threshold Register (PPFTTR, BAR4+14h) ............................................ 41
10.11 Parallel Port FIFO RX Threshold Register (PPFRTR, BAR4+15h) ............................................ 41
10.12 Auto Toggle Pin Select Register (ATPSR, BAR4+16h) ........................................................... 41
10.13 Parallel Port Interrupt Status Register (PPISR, BAR4+17h) ................................................... 42
10.14 PM_PME Message Resource Register (PPMRR, BAR4+18h) .................................................. 43
10.15 General Purpose Outputs Control Register (GPOCR, BAR4+20h) .......................................... 44
10.16 General Purpose Outputs Data Register (GPODR, BAR4+21h) .............................................. 45
10.17 Parallel Additional Function Register (PAFR, BAR4+23h) ...................................................... 45
11. UART(SB16C1050A) Functional Description ................................................................................... 46
11.1 FIFO Operation ................................................................................................................... 46