DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
4
11.2 Hardware Flow Control ........................................................................................................ 47
11.2.1 Auto-RTS .................................................................................................................. 47
11.2.2 Auto-CTS .................................................................................................................. 48
11.3 Software Flow Control ......................................................................................................... 49
11.3.1 Transmit Software Flow Control .................................................................................. 50
11.3.2 Receive Software Flow Control ................................................................................... 50
11.3.3 Xon Any Function ...................................................................................................... 53
11.3.4 Xoff Re-transmit Function ........................................................................................... 53
11.4 Sleep Mode with Auto Wake-Up ........................................................................................... 54
11.5 Programmable Baud Rate Generator .................................................................................... 54
11.6 Break and Time-out Conditions ............................................................................................ 56
11.7 Multi Drop Mode (9-bit Data Transmission) ........................................................................... 57
12.7.1 Transmit 9-bit Address Register (TAR) / Transmit 9-bit Data Register(TDR) ................... 59
11.7.2 Automatic Address Compare ....................................................................................... 61
11.7.3 Changed Register Map ............................................................................................... 62
12. UART Register Descriptions .......................................................................................................... 63
12.1 Transmit Holding Register (THR, Page 0) .............................................................................. 67
12.2 Receive Buffer Register (RBR, Page 0) .................................................................................. 67
12.3 Interrupt Enable Register (IER, Page 0) ................................................................................ 67
12.4 Interrupt Status Register (ISR, Page 0) ................................................................................ 68
12.5 FIFO Control Register (FCR, Page 0) .................................................................................... 69
12.6 Line Control Register (LCR, Page 0) ...................................................................................... 70
12.7 Modem Control Register (MCR, Page 0) ................................................................................ 71
12.8 Line Status Register (LSR, Page 0) ....................................................................................... 72
12.9 Auto Toggle Control Register (ACR, Page 0 & Page 1) ............................................................ 73
12.10 Modem Status Register (MSR, Page 0) ................................................................................ 73
12.11 Multi Drop mode Register (SPR, Page 0 & Page 1) ............................................................... 74
12.12 Scratch Pad Register (SPR, Page 0) .................................................................................... 75
12.13 Transmit 9-bit Address Register (TAR, Page 0) .................................................................... 75
12.14 Divisor Latches (DLL, DLM, Page 1) .................................................................................... 75
12.15 Transmit FIFO Count Register (TCR, Page 2) ....................................................................... 75
12.16 Receive FIFO Count Register (RCR, Page 2) ........................................................................ 75
12.17 Flow Control Status Register (FSR, Page 2) ......................................................................... 76
12.18 Page Select Register (PSR, Page 3) .................................................................................... 77