DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
40
10.9 Interrupt Poll Register (IPR, BAR4+10h)
IPR indicates interrupt generation state of Port 1 ~ Port 2.
Table 10–8: Interrupt Poll Register Description
Bit
Symbol
Description
7
IPR[7]
Not used.
6
IPR[6]
Interrupt Polling Bit for Parallel Port
0b: Parallel Port interrupt has occurred.
1b: Parallel Port interrupt has not occurred.
5
IPR[5]
Interrupt Polling Bit for 6
th
Serial Port
0b: Serial Port6(4
th
external UART) interrupt has occurred.
1b: Serial Port6(4
th
external UART) interrupt has not occurred.
4
IPR[4]
Interrupt Polling Bit for 5
th
Serial Port
0b: Serial Port5(3
rd
external UART) interrupt has occurred.
1b: Serial Port5(3
rd
external UART) interrupt has not occurred.
3
IPR[3]
Interrupt Polling Bit for 4
th
Serial Port
0b: Serial Port4(2
nd
external UART) interrupt has occurred.
1b: Serial Port4(2
nd
external UART) interrupt has not occurred.
2
IPR[2]
Interrupt Polling Bit for 3
rd
Serial Port
0b: Serial Port3(1
st
external UART) interrupt has occurred.
1b: Serial Port3(1
st
external UART) interrupt has not occurred.
1
IPR[1]
Interrupt Polling Bit for 2
nd
Serial Port
0b: Serial Port2(2
nd
internal UART) interrupt has occurred.
1b: Serial Port2(2
nd
internal UART) interrupt has not occurred.
0
IPR[0]
Interrupt Polling Bit for 1
st
Serial Port
0b: Serial Port1(1
st
internal UART) interrupt has occurred.
1b: Serial Port1(1
st
internal UART) interrupt has not occurred.