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DataSheet_SB16C1053APCI_v106

ManualsBrandsSystemBase ManualsElectronic ComponentsPCI to Dual UART and Single Parallel with MIO Bus Bridge Controller, 128-pin TQFP - 90pcs Bundle
41424344454647484950
SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
42
10.13 Parallel Port Interrupt Status Register (PPISR, BAR4+17h)
It indicates interrupt status of parallel port.
Table 10–12: Parallel Port Interrupt Status Register Description
Bit
Symbol
Description
7:5
PPISR[7:5]
Reserved. Hardwired to 000b.
4
PPISR[4]
COMP_NACK (This bit is adopted in Compatibility mode)
When CTRL[4] (Control Register Bit 4 of Parallel Port) is 1b, if NACK is 0b, it is set to 1b.
It indicates NACK interrupt occurred.
When NACK is 1b or CTRL[4] is 0b, it is cleared to 0b.
If parallel port isn’t in COMP mode or CTRL[4] is 0b in COMP mode, this bit always have
0b.
3
PPISR[3]
ECP_NACK (This bit is adopted in ECP mode)
When CTRL[4] (Control Register Bit 4 of Parallel Port) is 1b, if NACK is changed from 0b
to 1b, it is set to 1b. It indicates NACK interrupt occurred.
When PPISR is read or CTRL[4] is wrote by 0b, it is cleared to 0b.
If parallel port isn’t in ECP mode or CTRL[4] is 0b in ECP mode, this bit always have 0b.
2
PPISR[2]
ECP_NERR (This bit is adopted in ECP mode)
When ECR[4] (Extended Control Register Bit 4 of Parallel Port) is 0b, if NERR is
changed from 1b to 0b, it is set to 1b. It indicates NERR interrupt occurred.
When PPISR is read or ECR[4] is wrote by 1b, it is cleared to 0b.
If parallel port isn’t in ECP mode or ECR[4] is 1b in ECP mode, this bit always have 0b.
1
PPISR[1]
ECP_RX (This bit is adopted in ECP mode)
When ECR[2] (Extended Control Register Bit 2 of Parallel Port) is 0b, if the stacked data
in RX FIFO is more than RX FIFO trigger level, this bit is set to 1b. It indicates RX
interrupt occurred.
When PPISR or ECR is read or ECR[2] is wrote by 1b, it is cleared to 0b.
If parallel port isn’t in ECP mode or ECR[2] is 1b in ECP mode, this bit always have 0b.
0
PPISR[0]
ECP_TX (This bit is adopted in ECP mode)
When ECR[2] (Extended Control Register Bit 2 of Parallel Port) is 0b, if the stacked data
in TX FIFO is more than TX FIFO trigger level, this bit is set to 1b.
It indicates TX interrupt occurred.
When PPISR or ECR is read or ECR[2] is wrote by 1b, it is cleared to 0b.
If parallel port isn’t in ECP mode or ECR[2] is 1b in ECP mode, this bit always have 0b.