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DataSheet_SB16C1053APCI_v106

ManualsBrandsSystemBase ManualsElectronic ComponentsPCI to Dual UART and Single Parallel with MIO Bus Bridge Controller, 128-pin TQFP - 90pcs Bundle
41424344454647484950
SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
43
10.14 PM_PME Message Resource Register (PPMRR, BAR4+18h)
Select event signal to wakeup Root Complex in D3
hot
state.
Table 10–13: PME# Signal Resource Register Description
Bit
Symbol
Description
1
PSRR[1]
D3hot-I
0b: Interrupt is not selected as Wakeup Event for waking up Root Complex (default).
1b: Interrupt is selected as Wakeup Event for waking up Root Complex.
Whether interrupt is generated or not is determined by IMR. That is, some port can only
generate interrupt or any ports among all ports can generate interrupt. When interrupt
occurs, asserts PME# signal to Root Complex.
0
PSRR[0]
D3hot-W
0b: WAKEREQ pin is not selected as Wakeup Event for waking up Root Complex (default).
1b: WAKEREQ pin is selected as Wakeup Event for waking up Root Complex.
When 1b is received by any logic, asserts PME# signal to Root Complex.
If PSRR[1:0] is set as 11b which means both D3
hot
-Interrupt and D3
hot
-WAKEREQ are
set, PME# signal is asserted when only one of both events occurs.