DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
44
10.15 General Purpose Outputs Control Register (GPOCR, BAR4+20h)
GPOCR enables or disables GPO[7:0] to output ports respectively.
Table 10–14: GPIO Output Enable Register Description
Bit
Symbol
Description
7
GPOCR[7]
0b: DIR or MA0 isn’t output through DIR_INTF12_MA0 pin.
(default).
1b: DIR or MA0 is output through DIR_INTF12_MA0 pin.
It is decided by PORT[2:0] which signal is output.
6
GPOCR[6]
0b: RXEN1# isn’t output through RXEN1#_INTF11 pin.
(default).
1b: RXEN1# is output through RXEN1#_INTF11 pin.
5
GPOCR[5]
0b: TXEN1 isn’t output through TXEN1_INTF10 pin.
(default).
1b: TXEN1 is output through TXEN1_INTF10 pin.
4
GPOCR[4]
0b: PMES isn’t output through PMES_INTF02 pin.
(default).
1b: PMES is output through PMES_INTF02 pin.
3
GPOCR[3]
0b: RXEN0# isn’t output through RXEN0#_INTF01 pin.
(default).
1b: RXEN0# is output through RXEN0#_INTF01 pin.
2
GPOCR[2]
0b: TXEN0 isn’t output through TXEN0_INTF00 pin.
(default).
1b: TXEN0 is output through TXEN0_INTF00 pin.
1
GPOCR[1]
0b: GPOD1 isn’t output through OEM#_GPO1 pin.
(default).
1b: GPOD1 is output through OEM#_GPO1 pin.
0
GPOCR[0]
0b: GPOD0 isn’t output through GPO0 pin.
(default).
1b: GPOD0 is output through OEM#_GPO0 pin.
Cf. GPOCR[1:0] are outputs as General Purpose Outputs Control for selecting Serial Interface
Information. Please refer Table 10-4 and Table 10-5.