DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
47
And by FCR[5:4], XOFF Trigger Level can be selected to either 8, 16, 56, or 60, and
XON Trigger Level to either 0, 8, 16, or 56 by FCR[7:6]. You can verify XON and XOFF
Trigger Level by FUR and FLR. In 64-byte FIFO mode TTR and RTR are Read Only.
If you select 256-byte FIFO mode, you can experience more powerful features of
SB16C1050A. Setting both FCR[0] and AFR[0] to 1b will enable this mode. In this mode,
Transmit Data FIFO, Receive Data and Receive Status FIFO are 256 bytes. Interrupt
Trigger Level and XON, XOFF Trigger Level are controlled by TTR, RTR, FUR and FLR,
not by FCR[7:4]. That is, TTR, RTR, FUR and FLR can both read and write. You can
verify free space of Transmit FIFO and the number of characters received in Receive
FIFO by TCR, RCR and ISR[7:6].
While TX FIFO is full, the value sent to THR by CPU disappears. And while RX FIFO is
full, the data coming from external devices disappear as well, provided that flow control
function is not used.
For more information, refer to Register Description.
11.2 Hardware Flow Control
Hardware flow control is done by Auto-RTS and Auto-CTS. Auto-RTS and Auto-CTS can
be enabled/disabled independently by programming EFR[7:6]. If Auto-RTS is enabled, it
reports that it cannot receive more data by asserting RTS# when the amount of received
data in RX FIFO exceeds the written value in FUR. Then after the data stored in RX
FIFO is read by CPU, it reports that it can receive new data by deasseting RTS# when
the amount of existing data in RX FIFO is less than the written value in FLR. When
Auto-CTS is enabled and CTS# is cleared to 0b, transmitting data to TX FIFO has to be
suspended because external device has reported that it cannot accept more data. When
data transmission has been suspended and CTS# is set to 1b, data in TX FIFO is
retransmitted because external device has reported that it can accept more data. These
operations prevent overrun during communication and if hardware flow control is
disabled and transmit data rate exceeds RX FIFO service latency, overrun error occurs.
11.2.1 Auto-RTS
To enable Auto-RTS, EFR[6] should be set to 1b. Once enabled, RTS# outputs 0b. If the
number of received data in RX FIFO is larger than the value stored in FUR, RTS# will
be changed to 1b and if not, holds 0b. This state indicates that RX FIFO can accept
more data. After RTS# changed to 1b and reported to the CPU that it cannot accept
more data, the CPU reads the data in RX FIFO and then the amount of data in RX FIFO
reduces. When the amount of data in RX FIFO equals the value written in FLR, RTS#
changes to 0b and reports that it can accept more data. That is, if RTS# is 0b now,
RTS# is not changed to 1b until the amount in RX FIFO exceeds the value set in FUR.
But if RTS# is 1b now, RTS# is not changed to 0b until the amount in RX FIFO equals
the value written in FLR.
The value of FUR and FLR is determined by FIFO mode. If FCR[7:6] holds 00b, ’01’,
‘10’, and 11b, FUR stores 8, 16, 56, and 60, respectively. And if FCR[5:4] holds
00b, ’01’, ‘10’, and 11b, FLR stores 0, 8, 16, and 56, respectively in 64-byte FIFO. In
256-byte FIFO mode, users can write FUR and FLR values as they want and use them.
But the value of FUR must be larger than that of FLR. While Auto-RTS is enabled, you
can verify if RTS# is 0b or 1b by FSR[5]. If FSR[5] is 0b, RTS# is 0b and if 1b, RTS# is