DataSheet_SB16C1053APCI_v106

SB16C1053APCI

PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus

PCI to 2S+1P with MIO Bus Bridge

JULY 2013 REV 1.06

In general system to support 9-bit communication, when serial data is sent, software

command procedure is like below.

① Indicate transmitting address by setting 9

bit to ‘1’ through THR

② Write byte data in THR

③ Indicate transmitting data by clearing 9

bit to ‘0’ through THR

④ Write byte data in THR

⑤ End communication

But, if the way that we suggest is used, software command procedure is like below.

① Write byte data in TAR(7h) (9

bit is set to ‘1’)

② Write byte data in TDR(0h, same to THR) (9

bit is cleared to ‘0’)

③ End communication

If the way that we suggest is used, when 9-bit data is sent, software command procedure

is more simplified and twice writing is reduced when RS422 and RS485 communication

packet is transmitted. Because of this thing, the performance can be more improved and

the serial communication system efficiency can be more upgraded.

11.7.2 Automatic Address Compare

In SB16C1050A UART Core, 2 interrupt sources are added by providing 9-bit

communication.

First, if 9-bit serial information is sent in RBR, an interrupt is occurred to detecting 9-bit

address. Second, if data of SCR (Special Character Register) is same to 9-bit data, the

interrupt is occurred.

Figure 11–11: Address Auto Detection

Receive Shift Register (RSR)

Receive Data

Buffer

(RBR)

Error

Flags

LSR

Special Character Register

(SCR)

COMPARE

Matched 9-bit Address Interrupt

Detected 9-bit Address Interrupt