DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
74
3
MSR[3]
∆DCD Input Status:
0b: No change on CD# input (default).
1b: Indicates th t the DCD# input has changed state.
2
MSR[2]
∆RI Input Status:
0b: No change on RI# input (default).
1b: Indicates that the RI# input has changed state from 0b to 1b.
1
MSR[ ]
∆DSR Input Status:
0b: No change on DSR# input (deault).
1b: Indicates that the DSR# input has changed state.
0
MSR[0]
∆CTS Input Status:
0b: No change on CTS# input (deault).
1b: Indicates that the CTS# input has changed state.
12.11 Multi Drop mode Register (SPR, Page 0 & Page 1)
Address 6h is used for MSR (Modem Status Register) in the existent UART Core with
R/W permission. But we change to use address 6h with write permission to MDR (Multi
Drop mode Register). This is used for setting 9-bit transmission mode of multi drop in
RS422 and RS485 network.
Table 12–11: Multi Drop mode Register Description
Bit
Symbol
Description
7:4
MDR[7:4]
Reserved.
3
MDR[3]
9
th
Bit Polarity Select (NPS):
0b: when 9
th
bit is 0, it decide to get an address byte.
when 9
th
bit is 1, it decide to get a data byte.
1b: when 9
th
bit is 1, it decide to get an address byte. (default)
when 9
th
bit is 0, it decide to get a data byte.
2
MDR[2]
Reserved.
1
MDR[1]
Auto Multi-drop Enable (AME):
When bit5 of EFR is set to ‘1’, UART core compare received
address byte with Special Character (Xoff2) automatically in 9-bit
transmission mode.
0b: receiving byte is saved in RBR or RX FIFO irrespective of
address matching. (deault).
1b: automatic compare between Xoff2 register and receiving
address byte. If the receiving byte is same with Xoff2,
UART core save the received byte to RBR or RX FIFO. If it
is not same, the UART core discard the received byte.
0
MDR[0]
Multi Drop Enable (MDE):
0b: it works as normal mode (deault).
1b: Indicates that UART is working in 9
th
bit transmission mode.
In 9
th
bit transmission mode, when an address (9
th
=1) comes to
RBR or RX FIFO, Interrupt will take place.