DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
80
12.21 Special Character Register (SCR, Page 3)
When Bit0 of MDR is set to ‘1’ (9-bit transmission mode), Xoff2 register is used as
Special Character Register.
12.22 Additional Feature Register (AFR, Page 4)
AFR enables or disables the 256-byte FIFO mode and controls the global interrupt.
Table 12–16 shows AFR bit settings.
Table 12–16: Additional Feature Register Description
Bit
Symbol
Description
7:6
AFR[7:1]
Not used, always 000_0000b.
0
AFR[0]
256-byte FIFO Enable:
0b: 256-byte FIFO mode is disabled and this means
SB16C1050A operates as Non FIFO mode or 64-byte
FIFO mode (default).
1b: 256-byte FIFO mode is enabled and ISR[7:6] operates as
256-TX FIFO Empty and 256-RX FIFO Full.
12.23 Xoff Re-transmit Count Register (XRCR, Page 4)
XRCR operates only when Software flow control is enabled by EFR[3:0] and Xoff Re-
transmit function of MCR[2] is also enabled. And it determines the period of
retransmission of Xoff character. Table 12–17 shows XRCR bit settings.
Table 12–17: Xoff Re-transmit Count Register Description
Bit
Symbol
Description
7:2
XRCR[7:2]
Not used, always 0000_00b.
1:0
XRCR[1:0]
Xoff Re-transmit Count Select:
00b: Transmits Xoff character whenever the number of
received data is 1 during XOFF status. (default)
01b: Transmits Xoff character whenever the number of
received data is 4 during XOFF status.
10b: Transmits Xoff character whenever the number of
received data is 8 during XOFF status.
11b: Transmits Xoff character whenever the number of
received data is 16 during XOFF status.
12.24 Transmit FIFO Trigger Level Register (TTR, Page 4)
TTR operates only when 256-byte FIFO mode is enabled. It sets the trigger level of
256-byte TX FIFO for generating transmit interrupt. Interrupt is generated when the
number of data remained in TX FIFO after transmitting through TXD pin is less than the
value of TTR. Initial value is 80h, 1000_0000b. 0000_0000b should never be written. If
written, unexpected operation may occur.