DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
85
13.3 Nibble Mode
Nibble mode provides an asynchronous, reverse channel(peripheral-to-host) under the control of
the host. Data bytes are transmitted as two sequential, four-bit nibbles using four peripheral-to-
host status lines. When the host and/or peripheral do not support bi-directional use of the data
lines, Nibble Mode may be used with Compatibility mode to implement a bi-directional channel.
The two meds cannot be active simultaneously.
13.3.1 Pin Descriptions in the Nibble Mode
Table 13–7: Pin Description in Nibble Mode
Signal
Name
Type
Nibble Protocol Signal Description
STROBE#
O
STROBE: This value should be held negated by the host.
This signal is controlled via the CTRL register.
BUSY
I
PRINTER BUSY(PtrBusy): The peripheral drives this value to
transfer data bits 3 and 7 sequentially.
This signal is indicated via the STAT register.
ACK#
I
PRINTER CLOCK(PtrClk): The peripheral devices asserts ACK# to
indicate to the host that received data is available. The signal is
subsequently asserted to qualify data being sent to the host.
This is indicated via the STAT register.
SELECT
I
XFLAG: The peripheral device drives XFLAG to transfer data bits 1
and 5 sequentially. This signal is indicated via the STAT register.
PERROR
I
Acknowledge Data Request (AckDataReq): The peripheral device
asserts to acknowledge for HostBusy assertion. This signal is
initially high. It is subsequently used to transfer data bits 2 and 6
sequentially. This signal is indicated via the STAT register.
FAULT#
I
Data Available (DataAvail): The peripheral device asserts
DataAvail to indicate data availability. It is subsequently used to
transfer data bits 0 and 4 sequentially. This signal is indicated via
the STAT register.
INIT#
O
INITIALIZE: This signal is controlled via the CTRL register by host.
AUTOFD#
O
Host Busy(HostBusy): The host negates AUTOFDÝ (HostBusy) in
response to ACKÝ being asserted. This signal is subsequently
driven low to enable the peripheral to transfer data to the host.
AUTOFDÝ is then driven high to acknowledge receipt of byte data.
This signal is controlled via the CTRL register.
PD[7:0]
O
DATA: This 8-bit output data path to the peripheral Host data is
written to the peripheral attached to the parallel port interface on
these signal lines.
SLCTIN#
O
SELECT INPUT: This signal is controlled via the CTRL register.