DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
86
13.4 Byte Mode
BYTE MODE provides an asynchronous, byte wide, reverse channel (peripheral-to-host) using
the eight data lines of the interface for data and the control/status lines for handshaking. Byte
Mode may be used to implement a bi-directional channel, with the transfer direction controlled by
the host, when both host and peripheral support bi-directional use of the data lines. It is
compatible with IBM PS/2 hosts.
13.4.1 Pin Descriptions in the Byte Mode
Table 13–8: Pin Description in Byte Mode
Signal
Name
Type
Byte Protocol Signal Description
STROBE#
O
Host Clock (HostClk): This signal is strobed low by the host to
acknowledge receipt of data
BUSY
I
Printer Busy (PtrBusy): The peripheral asserts PtrBusy to provide
forward channel peripheral busy status. This is indicated via the
STAT register.
ACK#
I
Printer Clock (PtrClk): The peripheral asserts PtrClk to indicate to
the host that received data is available. The signal is subsequently
asserted to qualify data being sent to the host. This is indicated via
the STAT register.
SELECT
I
XFLAG: The peripheral asserts XFLAG to indicate that the device
is on line. This signal is indicated via the STAT register.
PERROR
I
Acknowledge Data Request (AckDataReq): This singal is initially
high. The peripheral drives this signal to acknowledge for
HostBusy assertion. This signal is indicated via the STAT register.
FAULT#
I
Data Availability (DataAvail): The peripheral asserts DataAvail to
indicate data availability. This signal is indicated via the STAT
register.
INIT#
O
INITIALIZE: This value should be held negated by the host.
This signal is controlled via the CTRL register.
AUTOFD#
O
Host Busy(HostBusy): The host negates HostBusy in response to
nACK being asserted.The signal is subsequently driven low to
enable the peripheral to transfer data to the host. nAUTOFD is
then driven high to acknowledge receipt of nibble data.
This signal is controlled via the CTRL register.
PD[7:0]
O
DATA: This 8-bit data bus is used for bi-directional data transfer.
SLCTIN#
O
SELECT INPUT: This signal is controlled via the CTRL register.