DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
90
13.6.2 Register Descriptions in the ECP Mode
Table 13–12: Basic Parallel Port Registers in ECP Mode
Address
(BAR2 +)
Abbreviation
Register Name
ECR[7:5]
Access
0h
ECPAFIFO
ECP Address
011
R/W
1h
STAT
Status Register
ALL
R
2h
CTRL
Control Register
ALL
R/W
The ECPAFIFO register provides a channel address to the peripheral depending on the state of
bit 7. This I/O address location is only used in ECP Mode (ECR bits [7:5]=011). In this mode,
bytes written to this register are placed in the parallel port FIFO and transmitted via PDOUT[7:0]
using the ECP protocol. Bit 7 should always be set to 1.
The description of STAT register is same with Status Register of 13.2.1 Register Descriptions in
the Compatibility Mode.
The description of CTRL register is same with Control Register of 13.2.1 Register Descriptions in
the Compatibility Mode.
Table 13–13: Extended Parallel Port Registers in ECP Mode
Address
(BAR3 +)
Abbreviation
Register Name
ECR[7:5]
Access
0h
SDFIFO
Standard Parallel Port
Data FIFO
010
R/W
0h
ECPDFIFO
ECP Data FIFO
011
R/W
0h
TFIFO
Test FIFO
110
R/W
0h
CFGA
ECP Configuration A
111
R/W
1h
CFGB
ECP Configuration B
111
R/W
2h
ECR
Extended Control Register
ALL
R/W
SDFIFO is used to transfer data from the host to the peripheral when the ECR register is set for
compatible FIFO mode (Bits [7:5] = 010). Data bytes written from the system to this FIFO are
transmitted by a hardware handshake to the peripheral using the standard Compatibility protocol.
For this register, bytes are placed in the parallel port FIFO using DATA[7:0] of MIO Bus and
transmitted via PD[7:0].
ECPDFIFO is used to transfer data from the host to the peripheral when the ECR register is set
for ECP mode (Bits [7:5] = 011). Data bytes written from the system to this FIFO are transmitted
by a hardware handshake to the peripheral using the ECP protocol.
The Test FIFO provides a test mechanism for the ECP Mode FIFO by allowing data to be read,
written in either direction between the system and this FIFO. This Test Mode is selected by
setting ECR[7:5] = 110.
The data is transferred purely through the microprocessor interface. It may appear on the parallel