DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
91
port data lines, but without any hardware handshake.
The Test FIFO does not stall when overwritten or underrun. Data is simply ignored or re-read.
The full and empty bits of the ECR register (bits 1 and 0) can however be used to ascertain the
correct state of the FIFO.
The CFGA register provides information about the ECP Mode implementation. It is a Read Only
register. Access to this register is enabled by programming the ECR register (ECR[7:5] = 111).
At reset CFGA is set to 10h. 10h indicates an 8-bit implementation.
The CFGB register checks the PINTR line to determine possible conflicts. It is a Read Only
register. Access to this register is enabled by programming the ECR register (ECR[7:5] = 111).
Table 13–14: Extended Parallel Port Register Description in ECP Mode
D7
D6
D5
D4
D3
D2
D1
D0
Data
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
ECPAFIFO
1
Address
STAT
BUSY#
ACK#
PE
SLCT
NERR
0
0
0
CTRL
0
PDIR
INTEN
SLCTIN
INIT#
AUTOFD
STROBE
SDFIFO
Parallel Port Data FIFO
ECPDFIFO
ECP Data FIFO
TFIFO
Test FIFO
CFGA
0
0
0
1
0
0
0
0
CFGB
0
PINTR
0
0
0
0
0
0
ECR
MODE
INTERR
0
SERVINT
FIFOF
FIFOE
The ECR register selects ECP mode, enables service and error interrupts and provides interrupt
status. The ECR provides FIFO empty and FIFO full status.
Table 13–15: ECP Mode Selection (ECR[7:5])
Mode
Description
000
This puts the parallel port into Compatibility Mode and resets the pointers to
the FIFO (but not its contents). Setting the direction bit in the CTRL register
does not affect the parallel port interface in this mode.
001
This puts the parallel port into Byte Mode and resets the pointers to the FIFO
(but not its contents). The outcome is similar to above except that the
direction bit selects forward or reverse transfers.
010
This puts the parallel port into ISA Compatible FIFO mode, which is the same
as mode 000 except that PWords are written to the FIFO. FIFO data is
automatically transmitted using the standard parallel port protocol.
Note, this mode should only be used when PDIR = 0.
011
This puts the port into ECP Mode. In the forward direction, bytes written to the
ECPDFIFO and ECPAFIFO locations are placed in the ECP FIFO and
transmitted automatically to the peripheral using ECP protocol. In the reverse
direction, bytes are transferred from PDIN [7:0] to the ECP FIFO.
100
This puts the port into EPP Mode.