DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
92
101
Reserved.
110
This selects an ECP Test Mode in which the FIFO is read and written purely
through the microprocessor interface.
111
This is places the interface into Configuration Mode. In this mode, the CFGA
and CFGB registers are accessible at 0h & 1h of BAR3 respectively.
Table 13–16: ECR[4:0] Description
Bit
Name
Description
4
INTERR
When 0, this bit enables error interrupts to the host when a high to low
transition occurs on the nERR signal.
3
-
Reserved.
2
SERVINT
If SERVINT = '1', all service interrupts are disabled.
SERVINT = '0' enables one of below two interrupts.
If PDIR = 0, the SERVINT bit will be set to '1' whenever there are
'WriteIntrThreshold' or more bytes free in the FIFO
If PDIR = 1, the SERVINT bit will be set to '1' whenever there are
'ReadIntrThreshold' or more valid bytes to be read from the FIFO
1
FIFOF
FIFO Full Status. This bit indicates when the FIFO is full.
0
FIFOE
FIFO Empty Status. This bit indicates when the FIFO is empty.
13.6.3 ECP Mode Operation
Prior to ECP operations, the host must negotiate on the parallel port to determine if the
peripheral supports the ECP protocol. This is carried out under program control in mode 000.
After negotiation, the following must be initialized:
▪ Set Direction = 0 (enabling drivers)
▪ Set Strobe = 0 (causes NSTROBE to default to de-asserted state)
▪ Set autoFd = 0 (causes NAUTOFD to default to de-asserted state)
▪ Set Mode = 011 (ECP Mode)
ECP address bytes or data bytes can be sent automatically by writing to the ECPAFIFO or
ECPDFIFO respectively.
It should be noted that all FIFO data transfers are byte wide and byte aligned. Address transfers
are also byte wide and are only permitted in the forward direction.
The host may switch directions by first switching to mode 001, negotiating for the forward or
reverse channel, setting direction to 1 or 0 and then setting mode 011. When PDIR = 1, the
hardware will handshake each ECP read data byte and will attempt to fill the FIFO. Bytes can
then be read from the ECPDFIFO providing it is not empty.
ECP transfers can also be achieved (slowly) by handshaking individual bytes under program
control in mode 001 or 000
Termination can only be executed while the bus is in the forward direction. So if the bus is in the
reverse direction when termination is required, it must first be set back to the forward direction.
ECP Mode supports two advanced features to improve the effectiveness of the protocol for some
applications. These features are implemented by allowing the transfer of normal 8-bit data or 8-