SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 1. Description SB16C1054 is a quad UART(Universal Asynchronous Receiver/Transmitter) with 256byte FIFO supporting maximum communication speed of 5.3Mbps. It offers flow control function by hardware or software and signal lines which can open or close the Tx/Rx input/output when communicating by RS-422 or RS-485.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 ■ DMA Signaling Capability for Both Received and Transmitted Data ■ Software Selectable Baud Rate Generator ■ Prescaler Provides Additional Divide-by-4 Function ■ Fast Data Bus Access Time ■ Programmable Sleep Mode ■ Programmable Serial Interface Characteristics - 5, 6, 7, or 8-bit Characters - Even, Odd, or No Parity Bit Generation and Detection - 1, 1.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 4.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 5.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 DCD3# 3 2 1 68 67 66 65 64 63 62 61 60 RI3# D3 4 RXD3 D4 INTSEL D5 5 VCC D6 6 D0 D7 7 D1 GND 8 D2 RI0# 9 RXD0 DCD0# 5.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 5.3 Pin Description Table 2: Pin Description Data Bus Interface Name Pin Type Description TQFP80 PLCC68 A0 48 34 I Address Bus Lines [2:0]. These 3 address lines select one A1 A2 47 46 33 32 I I of the internal registers in UART channel 0-3 during a data bus transaction. D0 D1 7 8 66 67 I/O I/O Data Bus Lines [7:0]. These pins are tri-state data bus for data transfer to or from the controlling CPU.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 Table 2: REV 1.05 Pin Description…continued Name Pin Type Description TQFP80 PLCC68 TXRDY0#/TXEN0 TXRDY1#/TXEN1 21 40 - O O Transmitter Ready 0, 1, 2, and 3/Tx Enable 0, 1, 2, and 3. These pins provide individual channel transmitter ready or TXRDY2#/TXEN2 TXRDY3#/TXEN3 61 80 - O O transmit enable. TXRDY0-3# are enabled when ATR[1:0] is cleared to ‘00’ (default state). If ATR[1:0] are set to ‘11’, TXRDY0-3# operate as TXEN0-3.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 Table 2: REV 1.05 Pin Description…continued Name Pin Type Description TQFP80 PLCC68 RTS0# RTS1# 26 35 14 22 O O Request to Send (active low). These pins indicate that the UART is ready to send data to the modem, and affect RTS2# RTS3# 66 75 48 56 O O transmit and receive operations only when Auto-RTS function is enabled. CTS0# CTS1# 23 38 11 25 I I Clear to Send (active low).
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 6. Functional Description The SB16C1054 UART is pin-to-pin compatible with the TL16C554 and ST16C654 UARTs. SB16C1054 offers 16C450 and 16C650 modes. When FIFO is enabled, it has a register configuration compatible with 64-byte FIFO and 16C654, so it becomes compatible with 16C654. If you enable 256-byte FIFO, you use the unique supreme function that SB16C1054 offers. It offers communication speed up to 5.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 to be suspended because external device has reported that it cannot accept more data. When data transmission has been suspended and CTS# is set to ‘1’, data in TX FIFO is retransmitted because external device has reported that it can accept more data. These operations prevent overrun during communication and if hardware flow control is disabled and transmit data rate exceeds RX FIFO service latency, overrun error occurs. 6.2.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 6.2.2 Auto-CTS Setting EFR[7] to ‘1’ enables Auto-RTS. If enabled, data in TX FIFO are determined to be transmitted or suspended by the value of CTS#. If ‘0’, it means external UART can receive new data and data in TX FIFO are transmitted through TXD pin. If ‘1’, it means external UART can not accept more data and data in TX FIFO are not transmitted. But data being transmitted by then complete transmission.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 6.3 Software Flow Control Software flow control is performed by Xon and Xoff character transmitting/accepting. Software flow control is enabled/disabled independently by programming EFR[3:0] and MCR[6:5, 2]. If TX software flow control is enabled by EFR[3:2], Xoff character is transmitted to report that data can not be accepted when the stored amount of data in RX FIFO exceeds the value in FUR.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 6.3.1 Transmit Software Flow Control To make Transmit Software Flow Control enabled, EFR[3:2] must be set to ‘01’, ‘10’ or ‘11’. Unlike Auto-RTS in which ‘0’ is outputted on RTS# when TX software flow control function is enabled, Xon character is not transmitted at first. If the amount of data in RX FIFO (written in ISR[6] and RCR) is less than the value in FUR, Xon character is not transmitted because Xon is in initial state.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 Tips for using Xon/Xoff character as two characters are as follows. ■ If received characters are Xon1, Xon1 and Xon2, RX flow control status becomes XON and previous Xon1 is ignored. ■ If received characters are Xoff1, Xoff1 and Xoff2, RX flow control status becomes XOFF and previous Xoff1 is ignored.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 Table 4: REV 1.05 Xon/Xoff Character Recognition Logic Table Xon1 Char. Xon2 Char. Xoff1 Char. Xoff2 Char. Recognition of Recognition of Xon Char. Xoff Char.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 6.3.3 Xon Any Function While RX Software flow control function is enabled, data in TX FIFO are transmitted when received Xon character and transmission is suspended when Xoff character is received. This status is called ‘XOFF status’. Transmission is re-started when status changes to ‘XON status’ by incoming Xon character or Xon Any function that changes status when any data arrives. Xon Any function is enabled if MCR[5] is set to ‘1’.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 6.4 Interrupts As there are four independent 1-channel UARTs in SB16C1054, so there are four interrupts. Interrupts are assigned INT0, INT1, INT2, and INT3 for each channel. Each interrupt has six prioritized level’s interrupt generation capability. The IER enables each of the six types of interrupts and INT signal in response to an interrupt generation.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 6.5 DMA Operation Transmitter and Receiver DMA operation is available through TXRDY#, RXRDY#, TXRDY[3:0]#, and RXRDY[3:0]#. There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by FCR[3]. In DMA mode 0 or FIFO disable (FCR[3] = 0), DMA occurs in single character transfer. In DMA mode 1, multi-character DMA transfers are managed to relieve the CPU for longer periods of time. 6.5.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 6.5.2 Block DMA transfer (DMA Mode 1) Transmitter: When the characters in TX FIFO are less than the trigger level that is set in TTR, TXRDY# or TXRDY[3:0] signal is asserted. When TX FIFO is full, TXRDY# or TXRDY[3:0]# signal is deasserted. Receiver: When the characters in RX FIFO are more than the trigger level that is set in RTR, RXRDY# or RXRDY[3:0] signal is asserted. When RX FIFO is empty, RXRDY# or RXRDY[3:0]# signal is deasserted.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 6.7 Programmable Baud Rate Generator The SB16C1054 has a programmable baud rate generator with a prescaler. The prescaler is controlled by MCR[7], as shown in Figure 7. The MCR[7] sets the prescaler to divide the clock frequency by 1 or 4. And the baud rate generator further divides this clock frequency by a programmable divisor (DLL and DLM) between 1 and (2 16 – 1) to obtain a 16X sampling rate clock of the serial data rate.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 Table 5: REV 1.05 Baud Rates Desired Baud Rate 16X Digit Divisor for Prescaler with Divide by 1 1.8432MHz 3.6864MHz 7.3728MHz 14.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 6.8 Break and Time-out Conditions Break Condition: Break Condition is occurred when TXD signal outputs ‘0’ and sustains for more than one character. It is occurred if LCR[6] is set to ‘1’ and deleted if ‘0’. If break condition is occurred when normal data are transmitted on TXD, break signal is transmitted and internal serial data are also transmitted, but they are not outputted to external TXD pin.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 7. Register Descriptions Each UART channel in the SB16C1054 has its own set of registers selected by address lines A2, A1, and A0 with a specific channel selected. The complete register set is shown on Table 7 and Table 8.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 Table 7: Address REV 1.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 Table 7: REV 1.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 Table 8: Addr. A[2:0] REV 1.05 Internal Registers Description Reg.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 Table 8: Addr. A[2:0] REV 1.05 Internal Registers Description…continued Reg.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 7.3 Interrupt Enable Register (IER, Page 0) IER enables each of the seven types of Interrupt, namely receive data ready, transmit empty, line status, modem status, Xoff received, RTS# state transition from low to high, and CTS# state transition from low to high. All interrupts are disabled if bit[7:0] are cleared. Interrupt is enabled by setting appropriate bits. Table 9 shows IER bit settings.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 7.4 Interrupt Status Register (ISR, Page 0) The UART provides multiple levels of prioritized interrupts to minimize software work load. ISR provides the source of interrupt in a prioritized manner. Table 10 shows ISR[7:0] bit settings. Table 10: Interrupt Status Register Description Bit Symbol Description 7 ISR[7] FCR[0]/256 TX FIFO Empty. When 256-byte FIFO mode is disabled (default). Mirror the content of FCR[0].
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 7.5 FIFO Control Register (FCR, Page 0) FCR is used for enabling the FIFOs, clearing the FIFOs, setting transmit/receive FIFO trigger level, and selecting the DMA modes. Table 11 shows FCR bit settings.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 7.6 Line Control Register (LCR, Page 0) LCR controls the asynchronous data communication format. The word length, the number of stop bits, and the parity type are selected by writing the appropriate bits to the LCR. Table 12 shows LCR bit settings. Table 12: Line Control Register Description Bit Symbol Description 7 LCR[7] Divisor Latch Enable. 0 : Disable the divisor latch (default). 1 : Enable the divisor latch.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 7.7 Modem Control Register (MCR, Page 0) MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem. Table 13 shows MCR bit settings. Table 13: Modem Control Register Description Bit Symbol Description 7 MCR[7] Clock Prescaler Select. 0 : Divide by 1 clock input (default). 6 MCR[6] 1 : Divide by 4 clock input.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 7.8 Line Status Register (LSR, Page 0) LSR provides the status of data transfers between the UART and the CPU. When LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX FIFO. The errors in a character are identified by reading LSR and then reading RBR. Reading LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO read pointer is incremented by reading the RBR.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 7.9 Modem Status Register (MSR, Page 0) MSR provides the current status of control signals from modem or auxiliary devices. MSR[3:0] are set to ‘1’ when input from modem changes and cleared to ‘0’ as soon as CPU reads MSR. Table 15 shows MSR bit settings. Table 15: Modem Status Register Description Bit Symbol Description 7 MSR[7] DCD Input Status. Complement of Data Carrier Detect (DCD#) input.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 7.12 Global Interrupt Control Register (GICR, Page 2) GICR is a register that internal four 16C1050 UARTs share to use. It is used when determining whether each interrupt generated at four 16C1050 UARTs are transmitted to global interrupts or not. Table 16 shows the GICR bit settings.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 7.14 Transmit FIFO Count Register (TCR, Page 2) TCR shows the number of characters that can be stored in TX FIFO. In 64-byte FIFO mode, it consists of only TCR[6:0]. If the number of characters that can be stored in TX FiFO is 0, it is shown as ‘0000_0000’ and if 64, it is shown as ‘0100_0000’. In 256-byte FIFO mode, it consists of ISR[7] + TCR[7:0].
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 the number of data received in RX FIFO at the first time is less than the value of FUR, or it means the number of data in RX FIFO was more than the value of FUR and after the CPU read them, the number of data that remains unread after the CPU read the data received in RX FIFO is less than or equal to the value of FLR. That is, UART transmits Xon character to report external device that it can receive more data.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 7.17 Page Select Register (PSR, Page 3) If BFh is written in LCR, registers in Page3 and Page4 can be accessed. PSR is used to determine which page to use. Table 19 shows PSR bit settings. Table 19: Page Select Register Description Bit Symbol Description 7:1 PSR[7:1] Access Key. When writing data on PSR to change page, Access Key must be correspondent.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 7.18 Auto Toggle Control Register (ATR, Page 3) ATR controls the signals for controlling input/output signals when using Line Interface as RS422 or RS485, so eliminates additional glue logic outside. Table 20 shows ATR bit settings. Table 20: Auto Toggle Control Register Description Bit Symbol Description 7 ATR[7] RXEN Polarity Select. 0 : Asserted output of RXEN is ‘0’. 1 : Asserted output of RXEN is ‘1’.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 7.19 Enhanced Feature Register (EFR, Page 3) EFR enables or disables the enhanced features of the UART. Table 21 shows EFR bit settings. Table 21: Enhanced Feature Register Description Bit Symbol Description 7 EFR[7] Auto-CTS Flow Control Enable. 0 : Auto-CTS flow control is disabled (default). 1 : Auto-CTS flow control is enabled. Transmission stops when CTS# pin is inputted ‘1’. Transmission resumes when CTS# pin is inputted ‘0’.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 7.23 Additional Feature Register (AFR, Page 4) AFR enables or disables the 256-byte FIFO mode and controls the global interrupt. Table 22 shows AFR bit settings. Table 22: Additional Feature Register Description Bit Symbol Description 7:6 AFR[7:6] Not used, always ‘00’. 5 AFR[5] Global Interrupt Polarity Select 0 : GINT pin outputs ‘0’ when interrupt is generated (default). 1 : GINT pin outputs ‘1’ when interrupt is generated.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 7.25 Transmit FIFO Trigger Level Register (TTR, Page 4) Operates only when 256-byte FIFO mode is enabled. It sets the trigger level of 256-byte TX FIFO for generating transmit interrupt. Interrupt is generated when the number of data remained in TX FIFO after transmitting through TXD pin is less than the value of TTR. Initial value is 128h, ‘1000_0000’ and ‘0000_0000’ must not be written. If written, unexpected operation may occur. 7.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 Table 24: REV 1.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 8. Programmer’s Guide The base set of registers that is used during high-speed data transfer has a straightforward access method. The extended function registers require special access bits to be decoded along with the address lines. The following guide will help with programming these registers. Note that the descriptions below are for individual register access.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 Table 25: REV 1.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 Table 26: REV 1.05 SB16C1054 Programming Guide Command Action Initialize Process 1. Set Baud Rate to 0001h Read LCR, then save in temp Set LCR to 80h Set DLL to 01h Set DLM to 00h Set LCR to temp 2. Set TTR to 20h Set LCR to BFh Set PSR to A5h Set TTR to 20h 3. Set RTR to 80h Set RTR to 80h 4. Enable 256-byte FIFO Set AFR to 01h 5. Set Line Control Register to 8-data but, Set PSR to A4h no parity, 1 stop bit Set LCR to 03h 6.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 Table 26: SB16C1054 Programming Guide…continued Command Action For (Cnt = 0; Cnt < temp3; Cnt++) 5. Read Data Read TX_Data from TX_User_Buffer 6. Output TX Set THR to TX_Data Return from Interrupt Service Routine Serial Input Process 1. RX Interrupt is generated and jumped to Interrupt Service Routine 2. Read ISR Read ISR, then save in temp1 3.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 9. Electrical Characteristics Absolute Maximum Ratings Symbol Parameter VCC Conditions Min Max Unit Supply voltage — 3.6 V VI Input voltage —0.5 5.5 V VO Output voltage GND + 0.1 VCC – 0.1 V Tamb Operating ambient temperature —40 +85 ℃ Tstg Storage temperature —60 +150 ℃ In free-air DC Electrical Characteristics Symbol Parameter Conditions 3.3V Unit Min Nom Max VCC Supply voltage 2.7 3.3 3.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 A[2:0] REV 1.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 RXDx START DATA(5-8) PARITY REV 1.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 10. Package Outline 80-Pin TQFP: Thin Plastic Quad Flat Package; Body 12 ⅹ 12 ⅹ 1.0 mm 0,27 0,17 9,50 12,00 14,00 1,05 0,95 1,20 MAX 0,10 0,50 0,75 0,45 0-7 1.00 Note : 1. All dimensions are in millimeters. 2. Falls within ANSI Y14.
SB16C1054 QUAD UART WITH 256-BYTE FIFO FEBRUARY 2009 REV 1.05 68-Pin PLCC: Plastic Leaded Chip Carrier 1. All dimensions are in inches (millimeters). 2. Falls within ANSI Y14.5-1982 56 0.469 (11,913) 0.441 (11,201) 0.021 (0,53) 0.013 (0,33) 0.050 (1,27) Note : 0.18 (4,57) MAX 0.120 (3,05) 0.090 (2,29) 0.02 (0,51) MIN 0.469 (11,913) 0.441 (11,201) 0.956 (24,282) 0.950 (24,130) 0.995 (25,273) 0.985 (25,019) 0.956 (24,282) 0.950 (24,130) 0.032 (0.081) 0.026 (0,66) 0.995 (25,273) 0.
