SB16C1054_Data Sheet_EN

SB16C1054
QUAD UART WITH 256-BYTE FIFO
FEBRUARY 2009 REV 1.0
5
26
Table 8: Internal Registers Description
Addr.
A[2:0]
Reg. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Page 0 Registers
0h THR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0h RBR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1h IER 0/CTS#
Interrupt
Enable
0/RTS#
Interrupt
Enable
0/Xoff
Interrupt
Enable
0/Sleep
Mode
Enable
Modem
Status
Interrupt
Enable
Receive
Line
Status
Interrupt
Enable
THR
Empty
Interrupt
Enable
Receive
Data
Available
Interrupt
Enable
2h ISR FCR[0]/
256-TX
FIFO
Empty
FCR[0]/
256-RX
FIFO
Full
Interrupt
Priority
Bit 5
Interrupt
Priority
Bit 4
Interrupt
Priority
Bit 3
Interrupt
Priority
Bit 2
Interrupt
Priority
Bit 1
Interrupt
Priority
Bit 0
2h FCR RX
Trigger
Level
(MSB)
RX
Trigger
Level
(LSB)
0/TX
Trigger
Level
(MSB)
0/TX
Trigger
Level
(LSB)
DMA
Mode
Select
TX FIFO
Reset
RX
FIFO
Reset
FIFO
Enable
3h LCR Divisor
Enable
Set
TX Brake
Set
Parity
Parity
Type
Select
Parity
Enable
Stop
Bits
Word
Length
Bit 1
Word
Length
Bit 0
4h MCR Clock
Select
Page 2
Select/Xoff
Re-Transmit
Access
Enable
0/Xon
Any
0/Loop
Back
OUT2/
INTx
Enable
OUT1/
Xoff Re-
Transmit
Enable
RTS# DTR#
5h LSR RX FIFO
Data
Error
THR &
TSR
Empty
THR
Empty
Receive
Break
Framing
Error
Parity
Error
Overrun
Error
Receive
Data
Ready
6h MSR DCD# RI# DSR# CTS# ∆ DCD# ∆ RI# ∆ DSR# ∆ CTS#
7h SCR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Page 1 Registers
0h DLL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1h DLM Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Page 2 Registers
1h GICR 0 0 0 0 0 0 0 Global
Interrupt
Mask
2h GISR Global
Interrupt
Mask
Status
0 0 0 CH 3
Interrupt
Status
CH 2
Interrupt
Status
CH 1
Interrupt
Status
CH 0
Interrupt
Status
5h TCR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
6h RCR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
7h FSR 0 0 TX HW
Flow
Control
Status
TX SW
Flow
Control
Status
0 0 RX HW
Flow
Control
Status
RX SW
Flow
Control
Status