SB16C1054_Data Sheet_EN

SB16C1054
QUAD UART WITH 256-BYTE FIFO
FEBRUARY 2009 REV 1.0
5
3
4. Block Diagram
Figure 1: Block Diagram
SIGNAL
CTS0#/DSR0#/DCD0#/RI0#
LOGIC
TXRDY3#/RXRDY3#
MODEM
REGISTER
RECEIVE
FLOW
REGISTER
UART 1
INTRRUPT
GENERATOR
CONTROL
INTERRUPT
RTS0#/DTR0#
LOGIC
CLOCK AND
XTAL2
TXRDY1#/RXRDY1#
CTS1#/DSR1#/DCD1#/RI1#
TXRDY2#/RXRDY2#
RECEIVE
SHIFT
SHIFT
RXD2
TRANSMIT
CTS2#/DSR2#/DCD2#/RI2#
TXD2
TXD0
XTAL1
RXD0
LOGIC
CONTROL
REGISTER
TXD1
TXRDY0#/RXRDY0#
UART 0
RXD1
FIFO
LOGIC
LOGIC
TXRDY#/RXRDY#
GLOBAL
RTS2#/DTR2#
RTS3#/DTR3#
FIFO
RESET
CS#[3:0]
RTS1#/DTR1#
REGISTER
D[7:0]
FLOW
CTS3#/DSR3#/DCD3#/RI3#
INT[3:0]
CONTROL
TRANSMIT
CONTROL
CLKSEL
REGISTER
UART 2
RXD3
LOGIC
CONTROL
UART 3
BAUD RATE
SB16C1054
LOGIC
CONTROL
CONTROL
DATA AND
IOR#/IOW#
A[2:0]
TXD3