SB16C1054_Data Sheet_EN

SB16C1054
QUAD UART WITH 256-BYTE FIFO
FEBRUARY 2009 REV 1.0
5
31
7.6 Line Control Register (LCR, Page 0)
LCR controls the asynchronous data communication format. The word length, the number
of stop bits, and the parity type are selected by writing the appropriate bits to the LCR.
Table 12 shows LCR bit settings.
Table 12: Line Control Register Description
Bit Symbol Description
7 LCR[7] Divisor Latch Enable.
0 : Disable the divisor latch (default).
1 : Enable the divisor latch.
6 LCR[6] Break Enable.
0 : No TX break condition output (default).
1 : Forces TXD output to ‘0’, for alerting the communication
terminal to a line break condition.
5 LCR[5] Set Stick Parity.
LCR[5:3] = xx0 : No parity is selected.
LCR[5:3] = 0x1 : Stick parity disabled. (default)
LCR[5:3] = 101 : Stick parity is forced to ‘1’.
LCR[5:3] = 111 : Stick parity is forced to ‘0’.
4 LCR[4] Parity Type Select.
LCR[5:3] =001 : Odd parity is selected.
LCR[5:3] =011 : Even parity is selected.
3 LCR[3] Parity Enabled.
0 : No parity (default).
1 : A parity bit is generated during the transmission and
the receiver checks for receive parity.
2 LCR[2] Number of Stop Bits.
LCR[2:0] = 0xx : 1 stop bit (word length = 5, 6, 7, 8).
LCR[2:0] = 100 : 1.5 stop bits (word length = 5).
LCR[2:0] = 11x or 1x1 : 2 stop bits (word length = 6, 7. 8).
1:0 LCR[1:0] Word Length Bits.
00 : 5 bits (default).
01 : 6 bits.
10 : 7 bits.
11 : 8 bits.