SB16C1054_Data Sheet_EN

SB16C1054
QUAD UART WITH 256-BYTE FIFO
FEBRUARY 2009 REV 1.0
5
39
7.18 Auto Toggle Control Register (ATR, Page 3)
ATR controls the signals for controlling input/output signals when using Line Interface as
RS422 or RS485, so eliminates additional glue logic outside. Table 20 shows ATR bit
settings.
Table 20: Auto Toggle Control Register Description
Bit Symbol Description
7 ATR[7] RXEN Polarity Select.
0 : Asserted output of RXEN is ‘0’.
1 : Asserted output of RXEN is ‘1’. (default)
6 ATR[6] RXEN Control Mode Select.
Only when ATR[1:0] is ‘11’;
0 : RXEN is outputted as same as ATR[7], irrespective of TXD
signal. (default)
1 : RXEN is outputted as same as ATR[7] when TXD signal is not
transmitting. And outputted as complement of ATR[7] when
TXD signal is transmitting.
5 ATR[5] TXEN Polarity Select.
0 : Asserted output of TXEN is ‘0’. (default)
1 : Asserted output of TXEN is ‘1’.
4 ATR[4] TXEN Control Mode Select.
0 : TXEN is outputted as same as ATR[5], irrespective of TXD
signal. (default)
1 : TXEN is outputted as complement of ATR[5] when TXD signal
is not transmitting, and outputted as same as ATR[5] when
TXD signal is transmitting..
3:2 ATR[3:2] Not used, always ‘00’.
1:0 ATR[1:0] Auto Toggle Enable.
00 : Auto toggle is disabled (default).
RTS#/TXEN, DTR#TXEN pin operate as RTS#, DTR#. If 80-
pin, each of TXRDY/TXEN, RXRDY/RXEN operates as
TXRDY, RXRDY.
01 : RTS#/TXEN pin operates as TXEN. DTR#/TXEN pin operates
as DTR#. If 80-pin, each of TXRDY/TXEN, RXRDY/RXEN
operates as TXRDY, RXRDY.
10 : DTR#/TXEN pin operates as TXEN. RTS#/TXEN operates as
RTS#. If 80-pin, each of TXRDY/TXEN, RXRDY/RXEN
operates as TXRDY, RXRDY.
11 : Only in 80-pin. TXRDY/TXEN, RXRDY/RXEN pin operates as
TXEN, RXEN. RTS#/TXEN, DTR#/TXEN operates as RTS#,
DTR#.