SB16C1054_Data Sheet_EN

SB16C1054
QUAD UART WITH 256-BYTE FIFO
FEBRUARY 2009 REV 1.0
5
41
7.23 Additional Feature Register (AFR, Page 4)
AFR enables or disables the 256-byte FIFO mode and controls the global interrupt.
Table 22 shows AFR bit settings.
Table 22: Additional Feature Register Description
Bit Symbol Description
7:6 AFR[7:6] Not used, always ‘00’.
5 AFR[5] Global Interrupt Polarity Select
0 : GINT pin outputs ‘0’ when interrupt is generated (default).
1 : GINT pin outputs ‘1’ when interrupt is generated.
4 AFR[4] Global Interrupt Enable
0 : INT0/GINT pin is selected to INT0 (default).
1 : INT0/GINT pin is selected to GINT.
3:1 AFR[3:1] Not used, always ‘000’.
0 AFR[0] 256-byte FIFO Enable.
0 : 256-byte FIFO mode is disabled and this means SB16C1054
operates as Non FIFO mode or 64-byte FIFO mode (default).
1 : 256-byte FIFO mode is enabled and ISR[7:6] operates as
256-TX FIFO Empty and 256-RX FIFO Full.
7.24 Xoff Re-transmit Count Register (XRCR, Page 4)
XRCR operates only when Software flow control is enabled by EFR[3:0] and Xoff Re-
transmit function of MCR[2] is also enabled. And it determines the period of
retransmission of Xoff character. Table 23 shows XRCR bit settings.
Table 23: Xoff Re-transmit Count Register Description
Bit Symbol Description
7:2 XRCR[7:2] Not used, always ‘0000_00’.
1:0 XRCR[1:0] Xoff Re-transmit Count Select
00 : Transmits Xoff character whenever the number of received
data is 1 during XOFF status. (default)
01 : Transmits Xoff character whenever the number of received
data is 4 during XOFF status.
10 : Transmits Xoff character whenever the number of received
data is 8 during XOFF status.
11 : Transmits Xoff character whenever the number of received
data is 16 during XOFF status.