SB16C1054_Data Sheet_EN

SB16C1054
QUAD UART WITH 256-BYTE FIFO
FEBRUARY 2009 REV 1.0
5
44
8. Programmer’s Guide
The base set of registers that is used during high-speed data transfer has a
straightforward access method. The extended function registers require special access
bits to be decoded along with the address lines. The following guide will help with
programming these registers. Note that the descriptions below are for individual register
access. Some streamlining through interleaving can be obtained when programming all
the registers.
Table 25: Register Programming Guide
Command Action
Set Baud Rate to VALUE1, VALUE2 Read LCR, then save in temp
Set LCR to 80h
Set DLL to VALUE1
Set DLM to VALUE2
Set LCR to temp
Set Xon1, Xoff1 to VALUE1, VALUE2 Read LCR, then save in temp
Set LCR to BFh
Set Xon1 to VALUE1
Set Xoff1 to VALUE2
Set LCR to temp
Set Xon2, Xoff2 to VALUE1, VALUE2 Read LCR, then save in temp
Set LCR to BFh
Set Xon2 to VALUE1
Set Xoff2 to VALUE2
Set LCR to temp
Set Software Flow Control Mode to VALUE Read LCR, then save in temp
Set LCR to BFh
Set EFR to VALUE
Set LCR to temp
Set flow control threshold for 64-byte FIFO
Mode
1) Set FCR to ‘0000_xxx1’
 Set FUR to 8, set FLR to 0
2) Set FCR to ‘0101_xxx1’
 Set FUR to 16, set FLR to 8
3) Set FCR to ‘1010_xxx1’
 Set FUR to 56, set FLR to 16
4) Set FCR to ‘1111_xxx1’
 Set FUR to 60, set FLR to 56
Set flow control threshold for 256-byte
FIFO Mode
Set FCR to ‘xxxx_xxx1’
Read LCR, then save in temp
Set LCR to BFh
Set PSR to A5h
Set AFR to 01h