SB16C1054_Data Sheet_EN

SB16C1054
QUAD UART WITH 256-BYTE FIFO
FEBRUARY 2009 REV 1.0
5
5
5.2 Pin Configuration for 68-Pin PLCC Package
Figure 3: 68-Pin PLCC Pin Configuration
58
DSR0#
DTR1#/TXEN1
A0
42
INT3
5
16
D0
GND
A1
4329
RTS3#/TXEN3
DCD0#
RXD0
6
17
D1
RTS1#/TXEN1
A2
59
44
30
GND
DCD3# RI0#
7 61
18
D2
INT1
NC
60
45
31
DTR3#/TXEN3
DSR2#
8 62
48
CS1#
CLKSEL
NC - No internal connection
46
32
CTS3#
CTS2#
63
TXD1
RXD1
DCD2#
47
33
19
DTR2#/TXEN2
D3
649
IOW#
RI1# RI2#
49
34
20
VCC
D4
65
TXD0
DCD1#
RXD2
50
35
21
RTS2#/TXEN2
D5
66
GND
51
36
22
INT2
D6
TXRDY#
52
37
23
RI3#
CS0#
10
67
DSR3#
RXRDY#
53
38
24
RXD3
INT0/GINT
11
CS2#
68
RESET
54
25
VCC
RTS0#/TXEN0
12
TXD2
1
55
26
INTSEL
VCC
39
13
IOR#
2
56
27
D7
DTR0#/TXEN0
DSR1#
XTAL2
40
14
TXD3
3
57
28
GND
CTS0#
CTS1#
XTAL1
41
15
CS3#
4