SB16C1054_Data Sheet_EN

SB16C1054
QUAD UART WITH 256-BYTE FIFO
FEBRUARY 2009 REV 1.0
5
50
t
rd
Pulse duration, IOR# low
24 ns
t
csr
Set up time, CSx# valid before IOR# low †
10 ns
t
ar
Set up time, A2~A0 valid before IOR# low †
10 ns
t
ra
Hold time, A2~A0 valid after IOR# high †
2 ns
t
rcs
Hold time, CSx# valid after IOR# high †
0 ns
t
frc
Delay time, t
ar
+t
rd
+t
rc
‡
54 ns
t
rc
Delay time, IOR# high to IOR# or IOW# low
20 ns
t
wr
Pulse duration, IOW#↓
24 ns
t
csw
Setup time, CSx# valid before IOW#↓
10 ns
t
aw
Setup time, A2~A0 valid before IOW#↓
10 ns
t
ds
Setup time, D7~D0 valid before IOW#↑
15 ns
t
wa
Hold time, A2~A0 valid after IOW#↑
2 ns
t
wcs
Hold time, CSx# valid after IOW#↑
2 ns
t
dh
Hold time, D7~D0 valid after IOW#↑
5 ns
t
fwc
Delay time, t
aw
+t
wr
+t
wc
54 ns
t
wc
Delay time, IOW#↑ to IOW# or IOR#↓
20 ns
t
rvd
Enable time, IOR#↓ to D7~D0 valid
24 ns
t
hz
Disable time, IOR# to D7~D0 released
4 ns
t
irs
Delay time, INTx↓ to TXDx↓ at start
8 24 RCLK
t
sti
Delay time, TXDx↓ at start to INTx↑
8 8 RCLK
t
si
Delay time, IOW# high or low (WR THR) to INTx↑
16 32 RCLK
t
sxa
Delay time, TXDx↓ at start to TXRDY#↓
8 RCLK
t
hr
Propagation delay time, IOW#(WR THR)↓ to INTx↓
12 ns
t
ir
Propagation delay time, IOR#(RD IIR)↑ to INTx↓
12 ns
t
wxi
Propagation delay time, IOW#(WR THR) ↓ to TXRDY#↑
10 ns
t
sint
Delay time, stop bit to INTx↑ or stop bit to RXRDY# or read RBR to set interrupt
1 RCLK
t
rint
Propagation delay time, Read RBR/LSR to INTx↓/LSR interrupt↓
12 ns
t
rint
Propagation delay time, IOR# RCLK↓ to RXRDY#↑
12 ns
t
mdo
Propagation delay time, IOW#(WR MCR)↑ to RTSx#, DTRx#↑
12 ns
t
sim
Propagation delay time, modem input CTSx#, DSRx#, and DCDx#↓↑ to INTx↑
12 ns
t
rim
Propagation delay time, IOR#(RD MSR)↑ to interrupt↓
3 ns
t
sim
Propagation delay time, Rix#↑ to INTx#↓
12 ns
† The internal address strobe is always in active state.
‡ In the FIFO mode, td1= xxns (min) between reads of the FIFO and the status register.