SB16C1054_Data Sheet_EN

SB16C1054
QUAD UART WITH 256-BYTE FIFO
FEBRUARY 2009 REV 1.0
5
51
t
t
ra
t
IOR#
t
CSx#
t
t
t
A[2:0]
VALID DATA
hz
VALID ADDRESS
D[7:0]
rvd
rc
IOW#
rd
rcs
ar
t
csr
t
ACTIVE
frc
Figure 10: Read Cycle Timing
fwc
wr
t
dh
ACTIVE
t t
wa
t
t
D[7:0]
t
wc
t
A[2:0]
t
VALID DATA
t
VALID ADDRESS
CSx#
aw
wcscsw
ds
IOW#
IOR#
Figure 11: Write Cycle Timing