SB16C1054_Data Sheet_EN

SB16C1054
QUAD UART WITH 256-BYTE FIFO
FEBRUARY 2009 REV 1.0
5
53
(FIFO AT OR ABOVE
t
(RD LSR)
sint
rint
IOR#
(RD RBR)
LSI INTERRUPT
(FCR6, 7 = 0, 0)
DATA(5-8)START
INTx(TRIGGER
IOR#
LEVEL INTERRUPT
Clock
Sample
rint
t
RXDx
t
TRIGGER LEVEL)
STOP
(FIFO BELOW
PARITY
TRIGGER LEVEL)
Figure 15: Receiver FIFO First Byte (Sets RBR) Timing
TRIGGER LEVEL
Clock
STOP
TRIGGER LEVEL)
sint
(RD LSR)
t
sint
t
IOR#
rint
(RD RBR)
t
rint
TRIGGER LEVEL)
t
RXDx
(FIFO AT OR ABOVE
Sample
INTERRUPT
TOP BYTE OF FIFO
(FIFO BELOW
READ FROM FIFO
LSI INTERRUPT
PREVIOUS BYTE
IOR#
TIMEOUT OR
Figure 16: Receiver FIFO After First Byte (After RBR Set) Timing