SB16C1054_Data Sheet_EN

SB16C1054
QUAD UART WITH 256-BYTE FIFO
FEBRUARY 2009 REV 1.0
5
6
5.3 Pin Description
Table 2: Pin Description
Data Bus Interface
Name Pin Type Description
TQFP80 PLCC68
A0
A1
A2
48
47
46
34
33
32
I
I
I
Address Bus Lines [2:0]. These 3 address lines select one
of the internal registers in UART channel 0-3 during a data
bus transaction.
D0
D1
D2
D3
D4
D5
D6
D7
7
8
9
11
12
13
14
15
66
67
68
1
2
3
4
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Data Bus Lines [7:0]. These pins are tri-state data bus for
data transfer to or from the controlling CPU.
IOR# 70 52 I Read Data (active low strobe). A valid low level on IOR# will
load the data of an internal register defined by address lines
A [2:0] onto the UART data bus for access by an external
CPU.
IOW# 31 18 I Write Data (active low strobe). A valid low level on IOW# will
transfer the data from external CPU to an internal register
that is defined by address lines A [2:0].
CS0#
CS1#
CS2#
CS3#
28
33
68
73
16
20
50
54
I
I
I
I
Chip Select 0, 1, 2, and 3 (active low). These pins enable
data transfers between the external CPU and the UART for
the respective channel.
INT0/GINT
INT1
INT2
INT3
27
34
67
74
15
21
49
55
O
O
O
O
Interrupt 0/Global Interrupt, Interrupt 1, 2, and 3. These pins
provide individual channel interrupts or global interrupt.
INT0-3 are enabled when MCR[3] is set to ‘1’ and AFR[4] is
cleared to ‘0’ (default state). But INT0 operates as GINT and
INT1-INT3 are disabled when AFR[4] is set to ‘1’.
INT0-3’s asserted state is active high, but GINT’s asserted
state is determined by AFR[5]. GINT’s asserted state is
active high when AFR[5] is set to ‘1’, and active low when
AFR[5] is cleared to ‘0’.
INTSEL 6 65 I Interrupt Select. When INTSEL is left open or low state, the
tri-state interrupts available on INT0-3 are enabled by
MCR[3]. But, when INTSEL is in high state, INT0-3 are
always enabled.