SB16C1054_Data Sheet_EN

SB16C1054
QUAD UART WITH 256-BYTE FIFO
FEBRUARY 2009 REV 1.0
5
7
Table 2: Pin Description…continued
Name Pin Type Description
TQFP80 PLCC68
TXRDY0#/TXEN0
TXRDY1#/TXEN1
TXRDY2#/TXEN2
TXRDY3#/TXEN3
21
40
61
80
-
-
-
-
O
O
O
O
Transmitter Ready 0, 1, 2, and 3/Tx Enable 0, 1, 2, and 3.
These pins provide individual channel transmitter ready or
transmit enable.
TXRDY0-3# are enabled when ATR[1:0] is cleared to ‘00’
(default state). If ATR[1:0] are set to ‘11’, TXRDY0-3#
operate as TXEN0-3.
TXRDY0-3# (active low) are asserted by TX FIFO/THR
status for transmit channels 0-3. TXEN0-3’s asserted state
is determined by ATR[5:4]. If ATR[4] is cleared to ‘0’, the
state holds the same value as ATR[5]. If ATR[4] is set to ‘1’,
it is the auto-toggling state based on ATR[5].
If these pins are unused, leave them unconnected.
RXRDY0#/RXEN0
RXRDY1#/RXEN1
RXRDY2#/RXEN2
RXRDY3#/RXEN3
20
41
60
1
-
-
-
-
O
O
O
O
Receiver Ready 0, 1, 2, and 3/Rx Enable 0, 1, 2, and 3.
These pins provide individual channel receiver ready or
receive enable.
RXRDY0-3# are enabled when ATR[1:0] is cleared to ‘00’
(default state). If ATR[1:0] is set to ‘11’, RXRDY0-3# are
changed to RXEN0-3.
RXRDY0-3# (active low) are asserted by RX FIFO/RBR
status for receive channels 0-3. RXEN0-3’s asserted state is
determined by ATR[7:6]. If ATR[6] is cleared to ‘0’, the state
holds the same value as ATR[7]. If ATR[6] is set to ‘1’, it is
the auto-toggling state based on ATR[7].
If these pins are unused, leave them unconnected.
TXRDY# 55 39 O Transmitter Ready (active low). This is asserted by TX
FIFO/THR status for transmit channels 0-3.
RXRDY# 54 38 O Receiver Ready (active low). This is asserted by RX
FIFO/RHR status for receive channels 0-3.
Modem and Serial I/O Interface
Name Pin Type Description
TQFP80 PLCC68
TXD0
TXD1
TXD2
TXD3
29
32
69
72
17
19
51
53
O
O
O
O
Transmit Data. These pins are individual transmit data
output. During the local loop-back mode, the TXD output pin
is disabled and TXD data is internally connected to the RXD
input.
RXD0
RXD1
RXD2
RXD3
17
44
57
4
7
29
41
63
I
I
I
I
Receive Data. These pins are individual receive data input.
During the local loop-back mode, the RXD input pin is
disabled and RXD data is internally connected to the TXD
output.