SB16C1058_Data Sheet_EN

ManualsBrandsSystemBase ManualsElectronic ComponentsOctal UART with 256 Byte TX/RX FIFO, 80-pin TQFP - 60pcs Bundle

SB16C1058

OCTAL UART WITH 256-BYTE FIFO

JULY 2013 REV 1.04

Octal-UART Controller

with 256-Byte FIFO

SB16C1058

Revision 1.04

SystemBase Co., Ltd.

Summary of content (66 pages)

PAGE 1
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 Octal-UART Controller with 256-Byte FIFO SB16C1058 Revision 1.04 SystemBase Co., Ltd.
PAGE 2
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 CONTENTS 1. Description ............................................................................................................................................... 5 2. Features .................................................................................................................................................... 5 3. Ordering Information ..............................................................................................
PAGE 3
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 7.2 Receive Buffer Register (RBR, Page 0) ...................................................................................... 34 7.3 Interrupt Enable Register (IER, Page 0) ..................................................................................... 35 7.4 Interrupt Status Register (ISR, Page 0) ...................................................................................... 36 7.5 FIFO Control Register (FCR, Page 0) ............
PAGE 4
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 10.4 AC Electrical Characteristics .................................................................................................... 61 11.Package Outline ...................................................................... 오류! 책갈피가 정의되어 있지 않습니다.
PAGE 5
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 1. Description SB16C1058 is a octal UART(Universal Asynchronous Receiver/Transmitter) with 256-byte FIFO supporting maximum communication speed of 5.3Mbps. It offers flow control function by hardware or software and signal lines which can open or close the Tx/Rx input/output when communicating by RS-422 or RS-485.
PAGE 6
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 ■ Programmable Serial Interface Characteristics - 5, 6, 7, or 8-bit Characters - Even, Odd, or No Parity Bit Generation and Detection - 1, 1.
PAGE 7
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 4.
PAGE 8
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 5.
PAGE 9
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 5.2 Pin Description Table 2: Pin Description Data Bus Interface Name Pin Type Description ADDR0 ADDR1 59 58 I I Address Bus Lines [7:0]. Address Bus Lines operates in two modes – Normal mode or MIO mode. ADDR2 ADDR3 57 56 I I In the normal mode(MODE=0b), A[5:0] are used and A[7:6] are not used.
PAGE 10
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 Table 2: REV 1.04 Pin Description…continued Name Pin Type Description TXRDY0#_TXEN0 TXRDY1#_TXEN1 72 84 O O Transmitter Ready/Tx Enable. These pins provide individual channel transmitter ready or transmit enable. TXRDY0-7# are enabled when TXRDY2#_TXEN2 TXRDY3#_TXEN3 100 110 O O ATR[1:0] is cleared to ‘00’ (default state). If ATR[1:0] are set to ‘11’, TXRDY0-7# operate as TXEN0-7.
PAGE 11
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 Table 2: Name REV 1.04 Pin Description…continued Pin Type Description CTS0# 70 I Clear to Send (active low). These pins indicate the modem is ready to CTS1# CTS2# 82 92 I I accept transmitted data from the UART, and affect transmit and receive operations only when Auto-CTS function is enabled. CTS3# CTS4# 108 120 I I CTS5# CTS6# 2 14 I I CTS7# 24 I DTR0# 69 O Data Terminal Ready (active low).
PAGE 12
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 Table 2: REV 1.04 Pin Description…continued Multiport I/O Interfaces Pin Type IDASY0 Name 34 I Daisy Chain Input [1:0]. Description IDASY1 33 I These pins are used only in MIO mode. SystemBase’s MIO Bus can be expanded up to 32 serial ports by 8 ports. The ports are managed with Daisy Chain in order for 8 ports’ install information to be automatically recognized. These pins are the input of Daisy Chain.
PAGE 13
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 Table 2: REV 1.04 Pin Description…continued Multiport I/O Interfaces Name MODE Pin Type 64 I Description UART Mode Input MODE = 0b : Normal UART mode MODE = 1b : MIO UART mode Other Interfaces Name Pin Type Description XIN_OSC 97 I Crystal or External Clock Input. XOUT 98 O Crystal or Buffered Clock Output. CLKSEL 94 I Clock Select. This pin selects the divide-by-1 or divide-by-4 prescalable clock.
PAGE 14
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 6. Functional Description SB16C1058 UART supports Normal mode in which the chip operates as other common Octal-UARTs and MIO mode which supports SystemBase’s MIO mode. The mode can be selected by MODE input. Furthermore, the UART supports 256-byte FIFO which enhances system performance and prevents Overrun Errors in multiple serial communication system.
PAGE 15
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 Table 3: REV 1.
PAGE 16
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 Interface configuration and panels. 16-port serial card and expandable 32-port serial card can be made. 16-port serial card is designed to expand 16 serial ports with two SB16C1058 Octal-UARTs connected to SB4002A by MIO Bus as shown in below diagram. 32-port serial card is designed as shown in below diagram. It is composed of one SB4002A and is capable of expanding by 8 ports using 8-port panels.
PAGE 17
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 6.3 FIFO Operation SB16C1058’s FIFO has two modes, 64-byte FIFO mode and 256-byte FIFO mode. Setting FCR[0] to ‘1’ enables FIFO, and if AFR[0] is set to ‘0’, it operates in 64-byte FIFO mode(default). In this mode, Transmit Data FIFO, Receive Data and Receive Status FIFO are 64 bytes. 64-byte FIFO mode allows you to select the Transmit Interrupt Trigger Level from 8, 16, 32, or 56. You can verify this Interrupt Trigger Level by TTR and RTR.
PAGE 18
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 ‘1’ now, RTS# is not changed to ‘0’ until the amount in RX FIFO equals the value written in FLR. The value of FUR and FLR is determined by FIFO mode. If FCR[7:6] holds ‘00’, ’01’, ‘10’, and ‘11’, FUR stores 8, 16, 56, and 60, respectively. And if FCR[5:4] holds ‘00’, ’01’, ‘10’, and ‘11’, FLR stores 0, 8, 16, and 56, respectively in 64-byte FIFO. In 256-byte FIFO mode, users can write FUR and FLR values as they want and use them.
PAGE 19
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 6.5 Software Flow Control Software flow control is performed by Xon and Xoff character transmitting/accepting. Software flow control is enabled/disabled independently by programming EFR[3:0] and MCR[6:5, 2]. If TX software flow control is enabled by EFR[3:2], Xoff character is transmitted to report that data can not be accepted when the stored amount of data in RX FIFO exceeds the value in FUR.
PAGE 20
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 6.5.1 Transmit Software Flow Control To make Transmit Software Flow Control enabled, EFR[3:2] must be set to ‘01’, ‘10’ or ‘11’. Unlike Auto-RTS in which ‘0’ is outputted on NRTS when TX software flow control function is enabled, Xon character is not transmitted at first. If the amount of data in RX FIFO (written in ISR[6] and RCR) is less than the value in FUR, Xon character is not transmitted because Xon is in initial state.
PAGE 21
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 character. ■ If Xon and Xoff character are set to same, both characters are treated as Xon character. Tips for using Xon/Xoff character as two characters are as follows. ■ If received characters are Xon1, Xon1 and Xon2, RX flow control status becomes XON and previous Xon1 is ignored. ■ If received characters are Xoff1, Xoff1 and Xoff2, RX flow control status becomes XOFF and previous Xoff1 is ignored.
PAGE 22
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 Table 5: REV 1.04 Xon/Xoff Character Recognition Logic Table Xon1 Char. Xon2 Char. Xoff1 Char. Xoff2 Char. Recognition of Recognition of 11h 11h 13h 13h Xon Char. Xoff Char.
PAGE 23
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 6.5.3 Xon Any Function While RX Software flow control function is enabled, data in TX FIFO are transmitted when received Xon character and transmission is suspended when Xoff character is received. This status is called ‘XOFF status’. Transmission is re-started when status changes to ‘XON status’ by incoming Xon character or Xon Any function that changes status when any data arrives. Xon Any function is enabled if MCR[5] is set to ‘1’.
PAGE 24
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 6.6 Interrupts As there are eight independent channel UARTs in SB16C1058, so there are eight internal interrupts. Interrupts are assigned internal interrupts: INT0, INT1, INT2, INT3, INT4, INT5, INT6 and INT7 for each channel. Each interrupt has six prioritized level’s interrupt generation capability. The IER enables each of the six types of interrupts and INT signal in response to an interrupt generation.
PAGE 25
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 6.7 DMA Operation Transmitter and Receiver DMA operation is available through TXRDY#, RXRDY#, TXRDY#[7:0], and RXRDY#[7:0]. There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by FCR[3]. In DMA mode 0 or FIFO disable (FCR[3] = 0), DMA occurs in single character transfer. In DMA mode 1, multi-character DMA transfers are managed to relieve the CPU for longer periods of time. 6.7.
PAGE 26
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 6.7.2 Block DMA transfer (DMA Mode 1) Transmitter: When the characters in TX FIFO are less than the trigger level that is set in TTR, TXRDY# or TXRDY#[7:0] signal is asserted. When TX FIFO is full, TXRDY# or TXRDY#[7:0] signal is deasserted. Receiver: When the characters in RX FIFO are more than the trigger level that is set in RTR, RXRDY# or RXRDY#[7:0] signal is asserted. When RX FIFO is empty, RXRDY# or RXRDY#[7:0] signal is deasserted.
PAGE 27
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 ■ RXD input receives the data start bit transition. ■ Data byte is loaded to the TX FIFO or THR. ■ CTS#, DSR#, DCD#, and RI# inputs are changed. REV 1.04 6.9 Programmable Baud Rate Generator The SB16C1058 has a programmable baud rate generator with a prescaler. The prescaler is controlled by MCR[7], as shown in Figure 7. The MCR[7] sets the prescaler to divide the clock frequency by 1 or 4.
PAGE 28
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 Table 6: REV 1.04 Baud Rates Desired Baud Rate 16X Digit Divisor for Prescaler with Divide by 1 1.8432MHz 3.6864MHz 7.3728MHz 14.
PAGE 29
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 6.9 Break and Time-out Conditions Break Condition: Break Condition is occurred when TXD signal outputs ‘0’ and sustains for more than one character. It is occurred if LCR[6] is set to ‘1’ and deleted if ‘0’. If break condition is occurred when normal data are transmitted on TXD, break signal is transmitted and internal serial data are also transmitted, but they are not outputted to external TXD pin.
PAGE 30
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 7. UART Register Descriptions Each UART channel in the SB16C1058 has its own set of registers selected by address lines A2, A1, and A0 with a specific channel selected. The complete register set is shown on Table 8 and Table 9.
PAGE 31
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 Table 9: Address REV 1.
PAGE 32
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 Table 9: REV 1.
PAGE 33
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 Table 9: Addr. A[2:0] REV 1.04 Internal Registers Description Reg.
PAGE 34
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 Table 9: Addr. A[2:0] REV 1.04 Internal Registers Description…continued Reg.
PAGE 35
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 7.3 Interrupt Enable Register (IER, Page 0) IER enables each of the seven types of Interrupt, namely receive data ready, transmit empty, line status, modem status, Xoff received, NRTS state transition from low to high, and CTS# state transition from low to high. All interrupts are disabled if bit[7:0] are cleared. Interrupt is enabled by setting appropriate bits. Table 10 shows IER bit settings.
PAGE 36
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 7.4 Interrupt Status Register (ISR, Page 0) The UART provides multiple levels of prioritized interrupts to minimize software work load. ISR provides the source of interrupt in a prioritized manner. Table 11 shows ISR[7:0] bit settings. Table 11: Interrupt Status Register Description Bit Symbol Description 7 ISR[7] FCR[0]/256 TX FIFO Empty. When 256-byte FIFO mode is disabled (default). Mirror the content of FCR[0].
PAGE 37
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 7.5 FIFO Control Register (FCR, Page 0) FCR is used for enabling the FIFOs, clearing the FIFOs, setting transmit/receive FIFO trigger level, and selecting the DMA modes. Table 12 shows FCR bit settings.
PAGE 38
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 7.6 Line Control Register (LCR, Page 0) LCR controls the asynchronous data communication format. The word length, the number of stop bits, and the parity type are selected by writing the appropriate bits to the LCR. Table 13 shows LCR bit settings. Table 13: Line Control Register Description Bit Symbol Description 7 LCR[7] Divisor Latch Enable. 0 : Disable the divisor latch (default). 1 : Enable the divisor latch. 6 LCR[6] Break Enable.
PAGE 39
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 7.7 Modem Control Register (MCR, Page 0) MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem. Table 14 shows MCR bit settings. Table 14: Modem Control Register Description Bit Symbol Description 7 MCR[7] Clock Prescaler Select. 0 : Divide by 1 clock input (default). 6 MCR[6] 1 : Divide by 4 clock input.
PAGE 40
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 7.8 Line Status Register (LSR, Page 0) LSR provides the status of data transfers between the UART and the CPU. When LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX FIFO. The errors in a character are identified by reading LSR and then reading RBR. Reading LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO read pointer is incremented by reading the RBR.
PAGE 41
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 7.9 Modem Status Register (MSR, Page 0) MSR provides the current status of control signals from modem or auxiliary devices. MSR[3:0] are set to ‘1’ when input from modem changes and cleared to ‘0’ as soon as CPU reads MSR. Table 16 shows MSR bit settings. Table 16: Modem Status Register Description Bit Symbol Description 7 MSR[7] DCD# Input Status. Complement of Data Carrier Detect (DCD#) input.
PAGE 42
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 7.12 Global Interrupt Control Register (GICR, Page 2) GICR is a register that internal eight 16C1050 UARTs share to use. It is used when determining whether each interrupt generated at eight 16C1050 UARTs are transmitted to global interrupts or not. Table 17 shows the GICR bit settings. Table 17: Global Interrupt Control Register Description Bit Symbol Description 7 GICR[7] Interrupt Mask for 8 UART channel th 0 : Interrupt Masking.
PAGE 43
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 1 : Interrupt Non-masking. Global interrupt is generated when the value of GISR[0] is ‘1’. 7.13 Global Interrupt Status Register (GISR, Page 2) GISR is a register that internal eight 16C1050 UARTs share to use. It is used to verify the generation status of each interrupt of eight 16C1050 UARTs when global interrupt function is enabled. Table 18 shows GISR bit settings.
PAGE 44
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 7.15 Receive FIFO Count Register (RCR, Page 2) RCR shows the number of characters that is stored in RX FIFO. In 64-byte FIFO mode, it consists of only RCR[6:0]. If the number of characters that is stored in RX FiFO is 0, it is shown as ‘0000_0000’ and if 64, it is shown as ‘0100_0000’. In 256-byte FIFO mode, it consists of ISR[6] + RCR[7:0].
PAGE 45
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 character to report external device that it cannot receive more data. If RX FIFO has space to store more data, new data are stored in RX FIFO but after it gets full, they are lost. For more details, refer to ‘6.3 Software Flow Control’. 3:2 FSR[3:2] Not used, always ‘00’. 1 FSR[1] RX Hardware Flow Control Status. 0 : When FIFO or Auto-CTS flow control is disabled.
PAGE 46
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 7.18 Auto Toggle Control Register (ATR, Page 3) ATR controls the signals for controlling input/output signals when using Line Interface as RS422 or RS485, so eliminates additional glue logic outside. Table 21 shows ATR bit settings. Table 21: Auto Toggle Control Register Description Bit Symbol Description 7 ATR[7] RXEN Polarity Select. 0 : Asserted output of RXEN is ‘0’. 1 : Asserted output of RXEN is ‘1’.
PAGE 47
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 7.19 Enhanced Feature Register (EFR, Page 3) EFR enables or disables the enhanced features of the UART. Table 22 shows EFR bit settings. Table 22: Enhanced Feature Register Description Bit Symbol Description 7 EFR[7] Auto-CTS Flow Control Enable. 0 : Auto-CTS flow control is disabled (default). 1 : Auto-CTS flow control is enabled. Transmission stops when CTS# pin is inputted ‘1’. Transmission resumes when CTS# pin is inputted ‘0’.
PAGE 48
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 7.23 Additional Feature Register (AFR, Page 4) AFR enables or disables the 256-byte FIFO mode and controls the global interrupt. Table 23 shows AFR bit settings. Table 23: Additional Feature Register Description Bit Symbol Description 7:6 AFR[7:6] Not used, always ‘00’. 5 AFR[5] Global Interrupt Polarity Select 0 : GINT pin outputs ‘0’ when interrupt is generated (default). 1 : GINT pin outputs ‘1’ when interrupt is generated.
PAGE 49
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 7.25 Transmit FIFO Trigger Level Register (TTR, Page 4) Operates only when 256-byte FIFO mode is enabled. It sets the trigger level of 256-byte TX FIFO for generating transmit interrupt. Interrupt is generated when the number of data remained in TX FIFO after transmitting through TXD pin is less than the value of TTR. Initial value is 128d, ‘1000_0000’. And ‘0000_0000’ must not be written. If written, unexpected operation may occur. 7.
PAGE 50
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.
PAGE 51
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 8. Option Register Descriptions SB16C1058 can be used as normal Octal-UART with Normal mode or expand up to 32 ports with SystemBase MIO mode. Option Register Set is provided to efficiently manage these ports in MIO mode. These Option Registers contain the control information to manage serial ports and handles the interrupts from 8 channels as vectors so that device drivers can quickly access and resolve them.
PAGE 52
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.
PAGE 53
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 8.3 Interface Information Register Table 28: Bit Name 7 0b 6 0b Interface Information Register Descriptions Hardwired to 0 Type of Serial Port Interface 0h: RS232 Interface 2h: RS485 Interface 5 I[1:0] 4 3 TRXEN[1:0] 2 1 0b 0 0b 1h: RS422 Interface 4h: Unknown In RS422/485 communication, set the signal line used as TX/RX Enable signal 0h: RTS 1h: DTR 2h: Exclusive signal line (TXEN/RXEN) 3h: Not Defined Hardwired to 0 8.
PAGE 54
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 8.5 Interrupt Poll Register In Normal Mode, UART’s internal registers can be accessed through CS# and UART’s GISR (Global Interrupt Status Register) is used for checking 8 UART channel’s interrupt status. GISR is the same register as IPR in this case. IPR access Option Register through OPT# control signal in MIO mode and GISR access UART internal Register through CS# or nUART signal.
PAGE 55
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 9. Programmer’s Guide The base set of registers that is used during high-speed data transfer has a straightforward access method. The extended function registers require special access bits to be decoded along with the address lines. The following guide will help with programming these registers. Note that the descriptions below are for individual register access.
PAGE 56
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.
PAGE 57
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 Table 31: REV 1.
PAGE 58
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 Table 32: SB16C1058 Programming Guide Command Action Initialize Process 1. Set Baud Rate to 0001h Read LCR, then save in temp Set LCR to 80h Set DLL to 01h Set DLM to 00h Set LCR to temp 2. Set TTR to 20h Set LCR to BFh Set PSR to A5h Set TTR to 20h 3. Set RTR to 80h Set RTR to 80h 4. Enable 256-byte FIFO Set AFR to 01h 5. Set Line Control Register to 8-data but, Set PSR to A4h no parity, 1 stop bit Set LCR to 03h 6.
PAGE 59
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 Table 32: REV 1.04 SB16C1058 Programming Guide…continued Command Action Else For (Cnt = 0; Cnt < temp3; Cnt++) 5. Read Data Read TX_Data from TX_User_Buffer 6. Output TX Set THR to TX_Data Return from Interrupt Service Routine Serial Input Process 1. RX Interrupt is generated and Jumped to Interrupt Service Routine 2. Read ISR Read ISR, then save in temp1 3.
PAGE 60
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 10. Electrical Characteristics 10.1 Absolute Maximum Ratings Table 32: Absolute Maximum Ratings Symbol Parameter Min Max Unit VDD DC Supply Voltage -0.5 7.0 V VIN Input Voltage -0.5 VDD + 0.5 V VOUT Output Voltage Range 0 VDD + 0.5 V TSTG Storage Temperature -65 150 ℃ Absolute maximum ratings are those values beyond which damage to the device may occur.
PAGE 61
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 10.
PAGE 62
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 tsim REV 1.04 Propagation delay time, RI# ↑ to INT ↓ 12 † The internal address strobe is always in active state. ‡ In the FIFO mode, td1= xxns (min) between reads of the FIFO and the status register.
PAGE 63
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 TXDx START DATA(5-8) PARITY STOP(1-2) REV 1.
PAGE 64
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.
PAGE 65
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.
PAGE 66
SB16C1058 OCTAL UART WITH 256-BYTE FIFO JULY 2013 REV 1.04 11.Package Outline 128-Pin TQFP: Thin Plastic Octal Flat Package; Body 20 ⅹ 20 ⅹ 1.2 mm 0.27 0.17 Figure 20: 1.05 MAX 1.20 MAX 0.10 0.5 15.5 20.0 22.0 SB16C1058 128-Pin TQFP Outline (Mechanical Drawing) Note : 1. All dimensions are in millimeters. 2. Falls within ANSI Y14.5-1982 66 0.75 0.45 1.