SB16C1058_Data Sheet_EN

SB16C1058
OCTAL UART WITH 256-BYTE FIFO
JULY 2013 REV 1.04
25
6.7 DMA Operation
Transmitter and Receiver DMA operation is available through TXRDY#, RXRDY#,
TXRDY#[7:0], and RXRDY#[7:0]. There are two modes of DMA operation, DMA mode 0
or DMA mode 1, selected by FCR[3].
In DMA mode 0 or FIFO disable (FCR[3] = 0), DMA occurs in single character transfer. In
DMA mode 1, multi-character DMA transfers are managed to relieve the CPU for longer
periods of time.
6.7.1 Single DMA transfer (DMA Mode 0/FIFO Disable)
Transmitter: There are no character in TX FIFO or THR. And the TXRDY#[7:0] signals will
be in assert state. TXRDY#[7:0] will switch to deassert state after one character is loaded
into TX FIFO or THR.
Receiver: There is at least one character in RX FIFO or RHR. And the RXRDY#[7:0]
signals will be in assert state. Once RXRDY# is asserted, RXRDY#[7:0] signal will switch
to deassert state when there are no more characters in RX FIFO or RBR.
Figure 5 shows TXRDY#, TXRDY#[7:0], RXRDY#, and RXRDY#[7:0] in DMA mode
0/FIFO disable.
Figure 5: TXRDY#/TXRDY#[7:0] and RXRDY#/RXRDY#[7:0] in DMA mode 0/FIFO disable.
01h
TCR
TX FIFO
Character #1
TCR
00h TX FIFO EMPTY
TXRDY#,
TXRDY[3:0]#
AT LEAST ONE
LOCATION FILLED
TXRDY#,
TXRDY[3:0]#
RCR
RCR
RX FIFO EMPTY
RX FIFO
00h
RXRDY#,
RXRDY[3:0]#
01h Character #1
RXRDY#,
RXRDY[3:0]#
AT LEAST ONE
LOCATION FILLED
EMPTY
SPACE
EMPTY
SPACE
ISR[7]
0
1
ISR[7]
ISR[6]
0
0
ISR[6]