SB16C1058_Data Sheet_EN

SB16C1058
OCTAL UART WITH 256-BYTE FIFO
JULY 2013 REV 1.04
26
6.7.2 Block DMA transfer (DMA Mode 1)
Transmitter: When the characters in TX FIFO are less than the trigger level that is set in
TTR, TXRDY# or TXRDY#[7:0] signal is asserted. When TX FIFO is full, TXRDY# or
TXRDY#[7:0] signal is deasserted.
Receiver: When the characters in RX FIFO are more than the trigger level that is set in
RTR, RXRDY# or RXRDY#[7:0] signal is asserted. When RX FIFO is empty, RXRDY# or
RXRDY#[7:0] signal is deasserted.
The figure 6 below shows TXRDY#, TXRDY#[7:0] and RXRDY#, RXRDY#[7:0] in DMA
mode 1.
Figure 6: TXRDY#/TXRDY#[7:0] and RXRDY#/RXRDY#[7:0] in DMA mode 1.
6.8 Sleep Mode with Auto Wake-Up
The SB16C1058 provides sleep mode operation to reduce its power consumption when
sleep mode is activated. Sleep mode is enabled when EFR[4] and IER[4] are set to ‘1’.
Sleep mode is activated when:
■
■
■
■
RXD input is in idle state.
CTS#, DSR#, DCD#, and RI# are not toggling.
The TX FIFO and TSR are in empty state.
No interrupt is pending except THR and time-out interrupts.
In sleep mode, the SB16C1058 clock and baud rate clock are stopped. Since most
registers are clocked using these clocks, the power consumption is greatly reduced.
Normal operation is resumed when:
TCR
TCR
ISR[6]
80h
RXRDY#,
RXRDY[3:0]#
RCR
0
TX FIFO
80h
ISR[7]
0 00h Character #1
TXRDY#,
TXRDY[3:0]#
ISR[6]
0
ISR[7]
RCR
0 RX FIFO EMPTY
TXRDY#,
TXRDY[3:0]#
RXRDY#,
RXRDY[3:0]#
00h
TX FIFO FULL
RX FIFO
Character #1
TTR
80h
Character #2
Character #256
Character #255
Character #128
Character #127
Character #2
Character #1
Character #127
EMPTY
SPACE
Character #128
TTR
80h
RTR
80h
80h
RTR
Character #2
EMPTY
SPACE
Character #127
Character #128