SB16C1058_Data Sheet_EN

SB16C1058
OCTAL UART WITH 256-BYTE FIFO
JULY 2013 REV 1.04
27
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RXD input receives the data start bit transition.
Data byte is loaded to the TX FIFO or THR.
CTS#, DSR#, DCD#, and RI# inputs are changed.
6.9 Programmable Baud Rate Generator
The SB16C1058 has a programmable baud rate generator with a prescaler. The
prescaler is controlled by MCR[7], as shown in Figure 7. The MCR[7] sets the prescaler to
divide the clock frequency by 1 or 4. And the baud rate generator further divides this clock
frequency by a programmable divisor (DLL and DLM) between 1 and (2
16
– 1) to obtain a
16X sampling rate clock of the serial data rate. The sampling rate clock is used by
transmitter for data bit shifting and receiver for data sampling.
The divisor of the baud rate generator is:
Divisor =
(
XTAL1 Crystal Input Frequency
)
Prescaler
(Desired Baud Rate x 16)
MCR[7] is cleared to ‘0’ (prescaler = 1), when CLKSEL input is in high state after reset.
MCR[7] is set to ‘1’ (prescaler = 4), when CLKSEL input is in low state after reset.
Figure 7: Prescaler and Baud Rate Generator Block Diagram
DLL and DLM must be written to in order to program the baud rate. DLL and DLM are the
least and most significant byte of the baud rate divisor, respectively. If DLL and DLM are
both zero, the SB16C1058 is effectively disabled, as no baud clock will be generated.
Table 6 shows the baud rate and divisor value for prescaler with divide by 1 as well as
crystal with frequency 1.8432MHz, 3.6864MHz, 7.3728MHz, and 14.7456MHz,
respectively.
Figure 8 shows the crystal clock circuit reference.
PROGAMMABLE
CLOCK
OSCILLATOR
LOGIC
LOGIC
DIVISOR
(DIVIDE BY 4)
MCR[7] = 0
BAUD RATE
XTAL2
REFERENCE
LOGIC
INTERNAL
(DIVIDE BY 1)
LOGIC
INTERNAL
BAUD RATE
CLOCK FOR
TRANSMITTER
AND
RECEIVER
PRESCALER
XTAL1
MCR[7] = 1
PRESCALER
GENERATOR