SB16C1058_Data Sheet_EN
SB16C1058
OCTAL UART WITH 256-BYTE FIFO
JULY 2013 REV 1.04
41
7.9 Modem Status Register (MSR, Page 0)
MSR provides the current status of control signals from modem or auxiliary devices.
MSR[3:0] are set to ‘1’ when input from modem changes and cleared to ‘0’ as soon as
CPU reads MSR. Table 16 shows MSR bit settings.
Table 16: Modem Status Register Description
Bit
Symbol
Description
7
MSR[7]
DCD# Input Status.
Complement of Data Carrier Detect (DCD#) input.
In loop back mode this bit is equivalent to OUT2 in the MCR.
6
MSR[6]
RI# Input Status.
Complement of Ring Indicator (RI#) input.
In loop back mode this bit is equivalent to OUT1 in the MCR.
5
MSR[5]
DSR# Input Status.
Complement of Data Set Ready (DSR#) input.
In loop back mode this bit is equivalent to DTR in the MCR.
4
MSR[4]
CTS# Input Status.
Complement of Clear To Send (CTS#) input.
In loop back mode this bit is equivalent to RTS in the MCR.
3
MSR[3]
Delta DCD# Input Status.
0 : No change on DCD# input (default).
1 : Indicates that the DCD# input state has changed.
2
MSR[2]
Delta RI# Input Status.
0 : No change on RI# input (default).
1 : Indicates that the RI# input state changed from ‘0’ to ‘1’.
1
MSR[1]
Delta DSR# Input Status.
0 : No change on DSR# input (deault).
1 : Indicates that the DSR# input state has changed.
0
MSR[0]
Delta CTS# Input Status.
0 : No change on CTS# input (deault).
1 : Indicates that the CTS# input state has changed.
7.10 Scratch Pad Register (SPR, Page 0)
This 8-bit Read/Write Register does not control the UART in anyway. It is intended as a
scratch pad register to be used by the programmer to hold data temporarily.
7.11 Divisor Latches (DLL, DLM, Page 1)
Two 8-bit registers which store the 16-bit divisor for generation of the clock in baud rate
generator. DLM stores the most significant part of the divisor, and DLL stores the least
significant part of the divisor. Divisor of zero is not recommended.
Note that DLL and DLM can only be written to before sleep mode is enabled, i.e., before
IER[4] is set. Chapter 6.7 describes the details of divisor latches.