SB16C1058_Data Sheet_EN

SB16C1058
OCTAL UART WITH 256-BYTE FIFO
JULY 2013 REV 1.04
53
8.3 Interface Information Register
Table 28: Interface Information Register
Bit
Name
Descriptions
7
0b
Hardwired to 0
6
0b
5
I[1:0]
Type of Serial Port Interface
0h: RS232 Interface 1h: RS422 Interface
2h: RS485 Interface 4h: Unknown
4
3
TRXEN[1:0]
In RS422/485 communication, set the signal line used as TX/RX Enable signal
0h: RTS 1h: DTR
2h: Exclusive signal line (TXEN/RXEN) 3h: Not Defined
2
1
0b
Hardwired to 0
0
0b
8.4 Interrupt Mask Register
In Normal Mode, UART’s internal registers can be accessed through CS# and UART’s
GICR (Global Interrupt Control Register) is used for configuring 8 UART channel’s
interrupt mask. GICR is the same register as IPR in this case.
IMR access Option Register through OPT# control signal in MIO mode and GICR access
UART internal Register through CS# or UART# signal. GICR and IMR are same region
and SB16C1058 provides different methods of accessing them.
Table 29: Interrupt Mask Register
Bit
Name
Descriptions
7
M7
1h: Enables Port8 Interrupt.
0h : Disables Port8 Interrupt. (default)
6
M6
1h: Enables Port7 Interrupt.
0h : Disables Port7 Interrupt. (default)
5
M5
1h: Enables Port6 Interrupt.
0h : Disables Port6 Interrupt. (default)
4
M4
1h: Enables Port5 Interrupt.
0h : Disables Port5 Interrupt. (default)
3
M3
1h: Enables Port4 Interrupt.
0h : Disables Port4 Interrupt. (default)
2
M2
1h: Enables Port3 Interrupt.
0h : Disables Port3 Interrupt. (default)
1
M1
1h: Enables Port2 Interrupt.
0h : Disables Port2 Interrupt. (default)
0
M0
1h: Enables Port1 Interrupt.
0h : Disables Port1 Interrupt. (default)