SB16C1058_Data Sheet_EN

SB16C1058
OCTAL UART WITH 256-BYTE FIFO
JULY 2013 REV 1.04
7
4. Block Diagram
Figure 1: Block Diagram
UART 2
INT[3:0]
LOGIC
RTS0#/DTR0#
IOR#/IOW#
TXRDY4#_TXEN4/RXRDY4#_RXEN4
RXD4
RTS4#/DTR4#
TXD4
UART 4 CTS4#/DSR4#/DCD4#/RI4#
RXD5
TXRDY5#_TXEN5/RXRDY5#_RXEN5
RTS5#/DTR5#
TXD5
CTS5#/DSR5#/DCD5#/RI5#UART 5
RXD6
TXRDY6#_TXEN6/RXRDY6#_RXEN6
RTS6#/DTR6#
TXD6
CTS6#/DSR6#/DCD6#/RI6#UART 6
TXRDY7#_TXEN7/RXRDY7#_RXEN7
RXD7
RTS7#/DTR7#
TXD7
UART 7 CTS7#/DSR7#/DCD7#/RI7#
TRANSMIT
REGISTER
SB16C1058
SIGNAL
LOGIC
TXRDY1#_TXEN1/RXRDY1#_RXEN1
CONTROL
XTAL2
UART 0
RTS1#/DTR1#
REGISTER
D[7:0]
RTS2#/DTR2#
UART 1
REGISTER
CLKSEL
TXRDY#/RXRDY#
CTS2#/DSR2#/DCD2#/RI2#
SHIFT
LOGIC
CONTROL
CONTROL
REGISTER
FIFO
RECEIVE
TXD1
RXD1
RXD2
LOGIC
LOGIC
RXD0
DATA AND
GENERATOR
TXRDY3#_TXEN3/RXRDY3#_RXEN3
TXRDY2#_TXEN2/RXRDY2#_RXEN2
CONTROL
FLOW
RXD3
FIFO SHIFT
REGISTER
CTS0#/DSR0#/DCD0#/RI0#
CONTROL
INTERRUPT
CONTROL
RTS3#/DTR3#
CTS1#/DSR1#/DCD1#/RI1#
TXD0
RECEIVE
TXD2
TRANSMIT
LOGIC
TXD3
INTRRUPT
A[2:0]
CLOCK AND
RESET
CTS3#/DSR3#/DCD3#/RI3#
CS#[3:0]
BAUD RATE
UART 3
TXRDY0#_TXEN0/RXRDY0#_RXEN0
XTAL1
FLOW
GLOBAL
LOGIC
MODEM
CONTROL