SB16C1058_Data Sheet_EN

SB16C1058
OCTAL UART WITH 256-BYTE FIFO
JULY 2013 REV 1.04
9
5.2 Pin Description
Table 2: Pin Description
Data Bus Interface
Name
Pin
Type
Description
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
59
58
57
56
55
54
51
50
I
I
I
I
I
I
I
I
Address Bus Lines [7:0].
Address Bus Lines operates in two modes – Normal mode or MIO mode.
In the normal mode(MODE=0b), A[5:0] are used and A[7:6] are not used.
A[5:3] are for the selection of 8 UART channels and A[2:0] are for the
internal registers of the selected UART channel.
In the MIO mode(MODE=1b), A[7:0] are all used. A[7:6] are for the
selection of 4 panels. A[5:0] are same as normal mode.
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
43
42
41
40
39
38
37
36
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Data Bus Lines [7:0].
These pins are tri-state data bus for data transfer to or from the
controlling CPU.
IOR#
48
I
Read Data (active low strobe). A valid low level on IOR# will load the data
of an internal register defined by address lines onto the UART data bus
for access by an external CPU.
IOW#
47
I
Write Data (active low strobe). A valid low level on IOW# will transfer the
data from external CPU to an internal register that is defined by address
lines.
CS#_UART#
46
I
Chip Select (active low). This pin enables data transfers between the
external CPU and the UART for the respective channel. In MIO mode,
this pin’s name is nUART and it does as nCS in normal mode.
OPT#
45
I
Option Select (active low). This pin used in MIO mode only and enables
data transfer between the external CPU and internal option registers.
If you don’t use this pin in normal mode, please pull-up this pin.
BUF#
44
O
Buffer Enable (active low). This pin used in MIO mode only. When
SB16C1058 output data to MIO bus, it can control the direction of bus
transceivers.
INT
49
O
Interrupt, This pin is a global interrupt for all 8 UART channels.
Each internal interrupt, INT0-7 are enabled when MCR[3] is set to ‘1’ and
AFR[4] is cleared to ‘0’ (default state).
INT’s asserted state is determined by AFR[5]. It’s asserted state is active
high when AFR[5] is set to ‘1’, and active low when AFR[5] is cleared to
‘0’.
The status of the 8 interrupts are shown on IPR(Interrupt Poll Register).
The interrupts are masked through IMR(Interrupt Mask Register) and
handled.