Technical Manual
Table Of Contents
- Vocoder and Controller Boards Detailed Theory of Operation
- Introduction to This Section
- General
- Vocoder Board
- Controller Board
- Switching Regulator
- RX Signal Path
- TX Signal Path
- Controller Bootstrap and Asynchronous Buses
- Vocoder Bootstrap
- SPI Bus Interface
- Universal Connector and Option Selects
- Keypad and Display Module
- Controls and Control Top Flex
- Controller Memory Map
- Vocoder Memory Map
- MCU System Clock
- DSP System Clock
- Radio Power-Up/ Power-Down Sequence
- Notes
- Secure Modules
- Disassembly/Reassembly Procedures
- Troubleshooting Procedures
- Troubleshooting Charts
- Troubleshooting Waveforms
- Troubleshooting Diagrams
10-13
Chart 11. 02/A0, ADSIC Checksum Failure
Synopsis
The ADSIC calculates a checksum of the
configuration bus data programmed
through the Host µC SPI interface. This
failure indicates some problem with the
data. It should be noted that this is a
non-fatal error as it happened. As the
ADSIC controls some of the functions of
the DSP memory mapping and
interrupts, some aspects of ADSIC
programming problems may cause a
general DSP hardware failure. Some
operation of the ADSIC can be
determined by looking for the 8KHz @
IRQB. This signal is present only after
the host µC has programmed the IC.
Partial operation of the device may point
to a missing supply connection. Basic
failure modes are as follows:
1) An open or short in the DSP address
or data bus and select lines may cause
an error in reading the checksum.
2) Missing or improper 2.4 MHz clock
reference.
3) Missing signal in the Host µC SPI
programming interface.
4) Open or missing analog or digital
supply at one or more IC pads.
5) General IC failure.
Fail 02/A0
ADSIC Checksum
Failure
Use ohmmeter to electrically
verify following signal
connections to source IC:
Signal @ U406 Source
D8-D23 U405
A0-A2,A13-A15 U405
PS*,RD*,WR* U405
SELx,RSTx U701
SPD,SCLK U701
1
VDDD,VDD1,VDD2,
VDD3 +5V
VDDAb,VDDA +5VA
VSSD,VSS1,VSS2,
VSS3 GND
2
VSSA,VSSAb AGND
ABI R414
1
Note: Finding an open at VDDx
may be difficult because of low
isolation between supply pins.
2
Also measure continuity
between GND and AGND through
jumper R510 on controller.
Connections
good?
Repair opens.
No
Verify 2.4MHz
reference clock at
U406 IDC per Fig.
W10
Clock
Present?
Verify SPI
programming
signals per Fig.
W6. initiated by
mode change.
Programming
signals
verified?
Verify U406-
RSTx goes high on
initial power up.
Reset high?
Replace U406.
Verify clock at
ABACUS
source and/or
fix connection.
Verify SPI operation
by verifying
programming of
synthesizer IC
initiated by a channel
change. If pass find
connection problems to
U406. A failure
indicates a software
problem or hardware
fault with U701.
No
Yes
Yes
No
Yes
MAEPF-26025-O
No
Yes
Replace U701.