Service Manual Part 1

  8
  
8 
Synthesiser IC201 (MC145158) receives channel and reference frequency information
from the microprocessor via a three line serial interface:
• DATA - synthesiser data: A counter: 7 bits
M counter: 10 bits
Ref. counter: 14 bits
• CLK - synthesiser clock
• ENABLE - synthesiser latch.
Once the data has been latched in, the synthesiser IC processes the incoming signals; f
in
from the prescaler IC and f
ref
from the temperature compensated crystal oscillator
(TCXO) operating at 12.8MHz. The TCXO signal is divided by the reference counter to
provide 5kHz, 6.25kHz or 12.5kHz at the phase detector. IC201 generates the modulus
control at the appropriate time to change the dividing factor for the prescaler. The phase
detector outputs are summed and fed via the integrator to the control line. The VCO fre-
quency increases with a positive change in control line voltage.
The synthesiser produces a signal called LCK-DET which is fed to the exciter after some
processing to prevent transmission when the synthesiser is out of lock. The LCK-DET
signal is also fed to the I/O bus of the control circuitry, where the signal is used for fea-
tures such as scanning. The time lapse between the synthesiser latch pulse and the lock
detect line going low is typically 15ms (maximum is 20ms).
The T2000 uses a dual point modulation system which allows the radio to be modulated
at frequencies below the loop filter cut-off frequency (approximately 400Hz). In this sys-
tem, modulation is supplied to both the VCO and TCXO. When both the reference and
VCO are modulated below the cut-off frequency of the loop filter, the phase detector
cannot detect a difference between f
in
, and f
ref
and will not generate corrective signals.
The modulation bandwidth is therefore dependent only on the audio and coupling cir-
cuits.