Integration Manual
Table Of Contents
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in 2G connected mode
- 1.5.1.3 VCC current consumption in 3G connected mode
- 1.5.1.4 VCC current consumption in LTE connected mode
- 1.5.1.5 VCC current consumption in cyclic low power idle mode / active mode
- 1.5.1.6 VCC current consumption in fixed active mode
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interfaces
- 1.9 Data communication interfaces
- 1.10 eMMC interface
- 1.11 Digital Audio interfaces
- 1.12 ADC interfaces
- 1.13 General Purpose Input/Output
- 1.14 Reserved pins (RSVD)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Jamming detection
- 1.15.3 IP modes of operation
- 1.15.4 Dual stack IPv4 and IPv6
- 1.15.5 Embedded TCP/IP and UDP/IP
- 1.15.6 Embedded FTP and FTPS
- 1.15.7 Embedded HTTP and HTTPS
- 1.15.8 SSL and TLS
- 1.15.9 Firmware update Over AT (FOAT)
- 1.15.10 Firmware update Over The Air (FOTA)
- 1.15.11 Power Saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for the external battery charging circuit
- 2.2.1.8 Guidelines for external charging and power path management circuit
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interfaces
- 2.6 Data communication interfaces
- 2.7 eMMC interface
- 2.8 Digital Audio interface
- 2.9 ADC interfaces
- 2.10 General Purpose Input/Output
- 2.11 Reserved pins (RSVD)
- 2.12 Module placement
- 2.13 Module footprint and paste mask
- 2.14 Thermal guidelines
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- 6 FCC Notes
- Appendix
- Glossary
- Related documents
- Revision history
- Contact
TOBY-L3 series - System Integration Manual
TSD-19090601 - R13 System Integration Manual Page 108 of 143
2.6.5 SDIO interface
2.6.5.1 Guidelines for SDIO circuit design
TOBY-L3 series modules include a 4-bit Secure Digital Input Output interface (SDIO_D0, SDIO_D1, SDIO_D2,
SDIO_D3, SDIO_CLK, SDIO_CMD), where the module acts as an SDIO host controller designed to
communicate with compatible u-blox short range radio communication modules by means of the open
CPU API
communicate with external SDIO devices by means of the open CPU API
Connection with u-blox short range radio communication modules
Figure 55 and Table 43 show an application circuit for connecting TOBY-L3 series cellular modules to u-
blox JODY-W2 short range radio communication modules supporting IEEE 802.11a/b/g/n/ac 1x1 data rates
for Wi-Fi:
The SDIO pins of the TOBY-L3 series cellular module are connected to the related SDIO pins of the u-
blox JODY-W2 short range radio communication module, with appropriate low value series damping
resistors to avoid reflections and other losses in signal integrity, which may create ringing and loss of a
square wave shape.
The most appropriate value for the series damping resistors on the SDIO lines depends on the specific
line lengths and layout implemented. In general, the SDIO series resistors are not strictly required, but
it is recommended to slow the SDIO signal, for example with 22 or 33 resistors, and avoid any
possible ringing problem without violating the rise / fall time requirements.
The V_INT supply output pin of the TOBY-L3 series cellular module is connected to the shutdown input
pin (SHDNn) of the LDO regulators providing the 1.8 V supply rails for the u-blox JODY-W2 module,
with appropriate pull-down resistors to avoid an improper switch-on of the Wi-Fi module before the
switch-on of the V_INT supply source of the cellular module SDIO interface pins.
The GPIO6 pin of the cellular module is connected to the active low full power down input pin (PDN)
of the u-blox JODY-W2 module, and the GPIO7 pin of the cellular module is connected to the
CORE_PDN of the u-blox JODY-W2 module, implementing the Wi-Fi enable function.
The UART2 (TXD2, RXD2) pins of the cellular module are connected to the LTE_COEXT (LTE_COEX_TX
and LTE_COEX_RX) pins of the u-blox JODY-W2 module, implementing the LTE-WIFI coexisting function.
The GPIO1 pin of the cellular module is connected to the WL_DEV_WAKE pin of the u-blox JODY-W2
module, implementing the waking up the JODY-W2 module by the cellular module.
The configuration pin (CFG) of the u-blox JODY-W2 module is connected to ground by means of a
proper pull-down resistor
The WLAN antenna RF input/output (ANT1) of the u-blox JODY-W2 Wi-Fi module is directly connected
to a Wi-Fi antenna considering that the u-blox JODY-W2 module integrates a 2.4 GHz BAW band pass
filter that enables co-existence with LTE RF signals.