Integration Manual
Table Of Contents
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in 2G connected mode
- 1.5.1.3 VCC current consumption in 3G connected mode
- 1.5.1.4 VCC current consumption in LTE connected mode
- 1.5.1.5 VCC current consumption in cyclic low power idle mode / active mode
- 1.5.1.6 VCC current consumption in fixed active mode
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interfaces
- 1.9 Data communication interfaces
- 1.10 eMMC interface
- 1.11 Digital Audio interfaces
- 1.12 ADC interfaces
- 1.13 General Purpose Input/Output
- 1.14 Reserved pins (RSVD)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Jamming detection
- 1.15.3 IP modes of operation
- 1.15.4 Dual stack IPv4 and IPv6
- 1.15.5 Embedded TCP/IP and UDP/IP
- 1.15.6 Embedded FTP and FTPS
- 1.15.7 Embedded HTTP and HTTPS
- 1.15.8 SSL and TLS
- 1.15.9 Firmware update Over AT (FOAT)
- 1.15.10 Firmware update Over The Air (FOTA)
- 1.15.11 Power Saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for the external battery charging circuit
- 2.2.1.8 Guidelines for external charging and power path management circuit
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interfaces
- 2.6 Data communication interfaces
- 2.7 eMMC interface
- 2.8 Digital Audio interface
- 2.9 ADC interfaces
- 2.10 General Purpose Input/Output
- 2.11 Reserved pins (RSVD)
- 2.12 Module placement
- 2.13 Module footprint and paste mask
- 2.14 Thermal guidelines
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- 6 FCC Notes
- Appendix
- Glossary
- Related documents
- Revision history
- Contact
TOBY-L3 series - System Integration Manual
TSD-19090601 - R13 System Integration Manual Page 110 of 143
SDIO pins of the SDIO device, with appropriate low value series damping resistors to avoid reflections and
other losses in signal integrity, which may create ringing and loss of a square wave shape.
The most appropriate value for the series damping resistors on the SDIO lines depends on the specific line
lengths and layout implemented. In general, the SDIO series resistors are not strictly required, but it is
recommended to slow the SDIO signal, for example with 22 or 33 resistors, and avoid any possible
ringing problem without violating the rise / fall time requirements.
R2
SDIO Device
SD_D0
SD_D1
SD_D2
SD_D3
SD_CLK
SD_CMD
TOBY-L3 series
SDIO_D0
66
SDIO_D1
68
SDIO_D2
63
SDIO_D3
67
SDIO_CLK
64
SDIO_CMD
65
R3
R4
R5
R6
GNDGND
R1
Figure 55: Application circuit for connecting TOBY-L3 series modules to a 1.8 V SDIO device
Reference
Description
Part Number - Manufacturer
R1, R2, R3, R4,
R5, R6
22 Resistor 0402 5% 0.1 W
RK73B1ETTP220J - KOA
Table 43: Components for connecting TOBY-L3 series modules to a 1.8 V SDIO device
☞ Do not apply voltage to any SDIO interface pin before the switch-on of SDIO interface supply source
(V_INT), to avoid latch-up of circuits and allow a proper boot of the module.
☞ The ESD sensitivity rating of SDIO interface pins is 1 kV (HMB according to JESD22-A114). A higher
protection level could be required if the lines are externally accessible and this can be achieved by
mounting a very low capacitance ESD protection (e.g. Tyco Electronics PESD0402-140 ESD) close to the
accessible points.
☞ If the SDIO interface pins are not used, they can be left unconnected on the application board.
2.6.5.2 Guidelines for SDIO layout design
The SDIO serial interface requires the same considerations regarding electro-magnetic interference as any
other high speed digital interface.
Keep the traces short, avoid stubs and avoid coupling with RF lines / parts or sensitive analog inputs, since
the signals can cause the radiation of some harmonics of the digital data frequency.