Integration Manual
Table Of Contents
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in 2G connected mode
- 1.5.1.3 VCC current consumption in 3G connected mode
- 1.5.1.4 VCC current consumption in LTE connected mode
- 1.5.1.5 VCC current consumption in cyclic low power idle mode / active mode
- 1.5.1.6 VCC current consumption in fixed active mode
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interfaces
- 1.9 Data communication interfaces
- 1.10 eMMC interface
- 1.11 Digital Audio interfaces
- 1.12 ADC interfaces
- 1.13 General Purpose Input/Output
- 1.14 Reserved pins (RSVD)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Jamming detection
- 1.15.3 IP modes of operation
- 1.15.4 Dual stack IPv4 and IPv6
- 1.15.5 Embedded TCP/IP and UDP/IP
- 1.15.6 Embedded FTP and FTPS
- 1.15.7 Embedded HTTP and HTTPS
- 1.15.8 SSL and TLS
- 1.15.9 Firmware update Over AT (FOAT)
- 1.15.10 Firmware update Over The Air (FOTA)
- 1.15.11 Power Saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for the external battery charging circuit
- 2.2.1.8 Guidelines for external charging and power path management circuit
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interfaces
- 2.6 Data communication interfaces
- 2.7 eMMC interface
- 2.8 Digital Audio interface
- 2.9 ADC interfaces
- 2.10 General Purpose Input/Output
- 2.11 Reserved pins (RSVD)
- 2.12 Module placement
- 2.13 Module footprint and paste mask
- 2.14 Thermal guidelines
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- 6 FCC Notes
- Appendix
- Glossary
- Related documents
- Revision history
- Contact
TOBY-L3 series - System Integration Manual
TSD-19090601 - R13 System Integration Manual Page 89 of 143
Additional components (R1, C1 and D1 in Figure 35) are needed at the ANT_DET pin as ESD protection.
The ANT1 / ANT2 pins must be connected to the antenna connector by means of a transmission line
with a nominal characteristic impedance as close as possible to 50 .
The DC impedance at the RF port for some antennas may be a DC open (e.g. linear monopole) or a DC
short to reference GND (e.g. PIFA antenna). For those antennas without the diagnostic circuit of Figure 35,
the measured DC resistance is always at the limits of the measurement range (respectively open or short),
and there is no means to distinguish between a defect on the antenna path with similar characteristics
(respectively: removal of linear antenna or RF cable shorted to GND for a PIFA antenna).
Furthermore, any other DC signal injected to the RF connection from an ANT connector to a radiating
element will alter the measurement and produce invalid results for antenna detection.
☞ It is recommended to use an antenna with a built-in diagnostic resistor in the range from 5 k to 30 k
to assure good antenna detection functionality and avoid a reduction of module RF performance. The
choke inductor should exhibit a parallel Self Resonance Frequency (SRF) in the range of 1 GHz to
improve the RF isolation of the load resistor.
For example:
Consider an antenna with a built-in DC load resistor of 15 k. Using the +UANTR AT command, the module
reports the resistance value evaluated from the antenna connector provided on the application board to
GND:
Reported values close to the used diagnostic resistor nominal value (i.e. values from 13 k to 17 k if
a 15 k diagnostic resistor is used) indicate that the antenna is properly connected.
Values close to the measurement range maximum limit (approximately 50 k) or an open-circuit
“over range” report (see the TOBY-L3 series AT Commands Manual [2]) means that that the antenna is
not connected or the RF cable is broken.
Reported values below the measurement range minimum limit (1 k) indicate a short to GND at the
antenna or along the RF cable.
Measurement inside the valid measurement range and outside the expected range may indicate an
incorrect connection, damaged antenna or wrong value of antenna load resistor for diagnostics.
The reported value could differ from the real resistance value of the diagnostic resistor mounted inside
the antenna assembly due to the antenna cable length, the antenna cable capacity or the measurement
method used.
☞ If the primary / secondary antenna detection function is not required by the customer application, the
ANT_DET pin can be left unconnected and the ANT1 / ANT2 pins can be directly connected to the
related antenna connector by means of a 50 transmission line as shown in Figure 34.