Integration Manual

TSD-19090601 - R15 Contents Page 15 of 143
Function
Pin Name
Pin No
I/O
Description
Remarks
TXD1
159
I /
I /
I /
I
UART1 data input /
SPI2 MISO /
I2S1 Receive Data In /
PCM1 Data In
1.8 V input, Circuit 103 (TXD) in ITU-T V.24,
alternatively configurable as SPI2 MISO, I2S1 Receive Data In
or PCM1 Data In by open CPU API or AT command.
Internal pull-up to V_INT enabled when UART1 data input.
See section 1.9.2 / 1.9.2.3 for functional description.
See section 2.6.2 / 2.6.3 for external circuit design-in.
CTS1
195
O /
O /
O /
O
UART1 CTS output /
SPI2 Chip Select /
I2S1 Serial Clock /
PCM1 Clock
1.8 V output, Circuit 106 (CTS) in ITU-T V.24,
alternatively configurable as SPI2 Chip Select, I2S1 Serial
Clock or PCM1 Clock by open CPU API or AT Command.
See section 1.9.2 for functional description.
See section 2.6.2 / 2.6.3 for external circuit design-in.
RTS1
193
I /
O /
O /
O
UART1 RTS input /
SPI2 Shift Clock /
I2S1 Chip Select /
PCM1 Data Out
1.8 V input, Circuit 105 (RTS) in ITU-T V.24,
alternatively configurable as SPI2 Shift Clock, I2S1 Chip
Select or PCM1 Data Out by open CPU API or AT Command.
Internal pull-up to V_INT enabled when UART1 RTS input.
See section 1.9.2 for functional description.
See section 2.6.2 / 2.6.3 for external circuit design-in.
UART2
RXD2
162
O
UART2 data output,
1.8 V output, Circuit 104 (RXD) in ITU-T V.24. Used only
for coexistence between LTE and WIFI.
See section 1.9.2.3 for functional description.
See section 2.6.2 for external circuit design-in.
TXD2
161
I
UART2 data input
1.8 V input, Circuit 103 (TXD) in ITU-T V.24.
Internal active pull-up to V_INT. Used only for
coexistence between LTE and WIFI
See section 1.9.2.3 for functional description.
See section 2.6.2 for external circuit design-in.
UART3
RXD3
19
O
UART3 data output
1.8 V output, Circuit 104 (RXD) in ITU-T V.24.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
TXD3
18
I
UART3 data input
1.8 V input, Circuit 103 (TXD) in ITU-T V.24.
Internal active pull-up to V_INT.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
SPI0
SPI_MOSI
174
O /
O
SPI0 Master Output
Slave Input /
UART4 Receive Data
1.8 V, SPI0 data output.
Alternatively configurable as UART4 Receive Data by Open
CPU or AT Command.
See section 1.9.3.1 for functional description.
See section 2.6.3 for external circuit design-in.
SPI_MISO
169
I /
I
SPI0 Master Input Slave
Output /
UART4 Transmit Data
1.8 V, SPI0 data input.
Alternatively configurable as UART4 Transmit Data by Open
CPU or AT Command.
See section 1.9.3.1 for functional description.
See section 2.6.3 for external circuit design-in.