User manual

RS232-ADC16/24
7 Register description
The device's configuration is handled via read/writeable holding registers. PIO
data is also available at these holding registers. ADC channels appear as read-
only input registers.
7.1 Holding registers
Register map : holding registers
Address Name Description
0x0000 REG_PIN_DIR Configuration of pin input/output direction
0x0001 REG_OUT_CFG Output mode selection
0x0002 REG_OUT_VAL Output pin levels
0x0003 REG_IN_VAL Input pin levels
0x0004 REG_VERSION Firmware version
1
0x000D REG_ADC_DEC ADC precision
0x000E REG_BAUD Baud rate selection
0x000F REG_SYSCLK System clock selection
1
implemented in version 1.11.
REG_PIN_DIR 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- - - - - - - - Dir
7
Dir
6
Dir
5
Dir
4
Dir
3
Dir
2
Dir
1
Dir
0
Dir
n
selects between pin input and pin output. A set bit configurates the
corresponding pin D
n
as output. Input pins have are internally pulled to high
level. The default value of this register is 0x0000.
REG_OUT_CFG 0x0001
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- - - - - - - - OM
7
OM
6
OM
5
OM
4
OM
3
OM
2
OM
1
OM
0
OM
n
programms its corresponding pin D
n
into either push-pull or open-drain
mode if D
n
is configurated as output pin. A logic zero selects open-drain mode.
Any changes to input pins are ignored. The default value of this register is
0x0000.
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