User manual

Hardware Description
9
5.3.1. NAND Flash
The StampA5D3x is equipped with a 256 MB NAND flash with 100000 erase and write
cycles. Customer specific adaptations are possible up to 1 GB on-board NAND flash. It is
connected to chip select three (NCS3) of the microcontroller.
NAND flash has a different organisation of transistors than the commonly used NOR flash.
While it allows a much higher density and thus an increase in storage capacity, there are
some differences which need to be kept in mind.
Typically, NAND flash is organized in pages and blocks, similar to hard disks. Pages are
512, 2048 or 4096 bytes in size, typical block sizes are 16, 128, 256 or 512 KB. Reading and
programming are performed on a page basis. Programming can only be done sequently
in one block.
Additionally, NAND flash requires bad block management, either by the driver software
or by a separate controller chip. Most NAND devices are shipped with bad blocks. These
are identified and marked according to a specified bad block strategy. Further bad blocks
may be detected during runtime. They are detected via an ECC (error correcting code). If
a bad block is detected, the data is written to a different, good block, and the bad block
table is updated. So the overall memory capacity gradually shrinks as more and more
blocks are marked bad.
This error detection is done by software like U-boot and Linux. Additionally, NAND flash is
subject to a limited number of write and erase cycles. These are typically 100.000 cycles
per block. So it is highly recomended to use wear levelling filesystems.
5.3.2. NOR Flash
Optional the StampA5D3x can be equipped with 64MB NOR flash. Please note that when
NOR flash is assembled pins 14 to 40 (PE0 - PE27) are used on the module itself and are
not available for other multiplexing (see AppendixD, StampA5D3X Pin Assignment).
Typically NOR flash is organized in blocks, similar to hard disks. Typical block sizes are
64, 128, 256 KB. NOR flash can be read and written randomly. This makes it possible to
use NOR flash as execute in place (XIP) memory. To erase already written data, the whole
block containing the data has to be erased.
NOR flash is subject to limited write and erase cycles. These are typically 100.000 cycles
per block. So it is highly recommended to use wear levelling file systems.
5.3.3. LPDDR-SDRAM
The StampA5D3x is equipped with 256MB LPDDR-SDRAM (Low power DDR-SDRAM).
Customer specific adaptations allow configurations up to 512MB.
DDR-SDRAM allows random access to any of its memory area and is volatile memory.
DDR-SDRAM (Double Data Rate) takes over data at the rising and falling edge of a clock
pulse, thus achieving almost twice the bandwidth than a similar connected SDRAM. It has
a synchronous interface, that means it waits for a clock signal before responding to control
inputs and is therefore synchronized with the CPU bus. The clock is used to drive a final