User manual

Hardware Description

• SMD Clock

• USB Host Clock (common for all three channels)

• USB Device Clock

• Programmable Clocks

The PMC status register provides "Clock Ready" or, respectively, "PLL Lock" status bits

for each of these clocks. An interrupt is generated when any of these bits changes from

0 to 1. The PMC provides status flags for the

• Main Oscillator

• Master Clock

• PLLA

• PLLB

• Programmable Clocks

The Main Oscillator frequency can be measured by using the PMC Main Clock Frequency

5.10.2. Power Management

Using power management can dramatically reduce the power consumption of an

Embedded Device. Via the PMC various clocks can be disabled or their speed can be

reduced:

• stopping the PLLs (PLLA and / or PLLB)

• stopping the clocks of the various peripherals

• reducing the clock rates of peripherals, especially by changing MCK.

The PMC supports the following power-saving features: Idle mode and power-down mode.

Please note that not every operating system supports these modes.

• Idle Mode. In idle mode, the processor clock will be re-enabled by any interrupt. The

peripherals, however, are only able to generate an interrupt if they still have a clock, so

care has to be taken as to when a peripheral can be powered down.

• Power-down Mode. In many cases a system waits for a user action or some other

rare event. In such a case, it is possible to change MCK to SLCK. Any external event

which changes the state on peripheral pins (not the USB) can then be detected by the

PIO controller or the AIC.

It should also be taken into account that when a PLL is stopped it will take some time to

restart it. Changing the PLL frequencies or stopping them can therefore be done only

at a moderate rate. If short reaction times are required, this is not a choice.