User manual

Hardware Description
16
The PIT is intended for use as the operating system’s scheduler interrupt.
5.14. Watchdog Timer
The watchdog timer is a 12-bit timer running at 256 Hz (Slow Clock / 128). The maximum
watchdog timeout period is therefore equal to 16 seconds. If enabled, the watchdog
timer asserts a hardware reset at the end of the timeout period. The application program
must always reset the watchdog timer before the timeout is reached. If an application
program has crashed for some reason, the watchdog timer will reset the system, thereby
reproducing a well defined state once again.
The Watchdog Mode Register can be written only once. After a processor reset, the
watchdog is already activated and running with the maximum timeout period. Once the
watchdog has been reconfigured or deactivated by writing to the Watchdog Mode Register,
only a processor reset can change its mode once again.
5.15. Real-time Clock (RTC)
The Real-time clock combines a complete time-of-day clock with alarm, a two-hundred-
year Gregorian calendar and a programmable periodic interrupt. The time and calendar
values are coded in BCD format.
5.16. DMA Controller (DMAC)
The DMA Controller (DMAC) supports the following transfer schemes:
• Peripheral-to-Memory
• Memory-to-Peripheral
• Peripheral-to-Peripheral
• Memory-to-Memory
The DMAC contains unidirectional and bidirectional channels. The full-duplex peripherals
feature unidirectional channels used in pairs (transmit only or receive only). The half-
duplex peripherals feature one bidirectional channel. Typically full-duplex peripherals are
USARTs, SPI or SSC. The HSMCI is a half duplex device.
The SAMA5 microcontrollers have two DMA controllers connected to the AMBA peripheral
bridge. DMAC0 handles transfers between peripherals and memory from peripherals
connected on APB0 ( AMBA Peripheral Bridge 0).
Instance T/R Channel Interface Number
HSMCI0 Receive/Transmit 0
SPI0 Transmit 1
SPI0 Receive 2
USART0 Transmit 3
USART0 Receive 4
USART1 Transmit 5