User manual
Hardware Description
17
Instance T/R Channel Interface Number
USART1 Receive 6
TWI0 Transmit 7
TWI0 Receive 8
TWI1 Transmit 9
TWI1 Receive 10
UART0 Transmit 11
UART0 Receive 12
SSC0 Transmit 13
SSC0 Receive 14
SMD Transmit 15
SMD Receive 16
Table5.4.DMAC0 Channels Definition
DMAC1 handles transfers between peripherals and memory from peripherals connected
on APB1 ( AMBA Peripheral Bridge 1).
Instance T/R Channel Interface Number
HSMCI1 Receive/Transmit 0
HSMCI0 Receive/Transmit 1
ADC Receive 2
SSC1 Transmit 3
SSC1 Receive 4
UART1 Transmit 5
UART1 Receive 6
USART2 Transmit 7
USART2 Receive 8
USART3 Transmit 9
USART3 Receive 10
TWI2 Transmit 11
TWI2 Receive 12
DBGU Transmit 13
DBGU Receive 14
SPI1 Transmit 15
SPI1 Receive 16
SHA Transmit 17
AES Transmit 18
AES Receive 19
TDES Transmit 20
TDES Receive 21
Table5.5.DMAC1 Channels Definition
Using the DMAC removes processor overhead by reducing its intervention during the
transfer. This significantly reduces the number of clock cycles required for a data transfer,