User manual
Hardware Description
10
state machine in the chip, which allows to accept new instructions, before the previous
one has finished executing.
5.3.4. SRAM
The StampA5D3x is equipped with 128 KB internal SRAM. The internal SRAM can be
accessed in one bus cycle and may be used for time critical sections of code or interrupt
handlers.
5.4. Bus Matrix
The bus matrix of AT91SAM-controllers allows many master and slave devices to be
connected independently of each other. Each master has a decoder and can be defined
specially for each master. This allows concurrent access of masters to their slaves
(provided the slave is available).
The bus matrix is thus the bridge between external devices connected to the EBI, the
microcontroller's embedded peripherals and the CPU core.
Master 0 Cortex A5
Master 1 DMA Controller 0
Master 2 DMA Controller 0
Master 3 DMA Controller 0
Master 4 DMA Controller 1
Master 5 DMA Controller 1
Master 6 DMA Controller 1
Master 7 Gigabit Ethernet MAC DMA
Master 8 LCD DMA
Master 9 LCD DMA
Master 10 USB Host High Speed EHCI DMA
Master 11 USB HOST OHCI DMA
Master 12 USB Device High Speed DMA
Master 13 Ethernet MAC DMA
Master 14 ISI Controller DMA
Table5.1.Bus Matrix Masters
Slave 0 Internal SRAM 0
Slave 1 Internal SRAM 1
Slave 2 NFC SRAM
Slave 3 Internal ROM
Slave 4 Soft Modem (SMD)
UDP High Speed Dual RAM
USB OHCI
Slave 5
USB EHCI
Slave 6 External Bus Interface