User manual
Hardware Description
13
5.9. Clock Generation
5.9.1. Processor Clocks
The AT91SAMA5D3x has no PLLB, but provides the 480 MHz USB Clock via a UPLL.
The CPU generates its clock signals based on two crystal oscillators: One slow clock
(SLCK) oscillator running at 32.768 KHz and one main clock oscillator running at 18.432
MHz. The slow clock oscillator also serves as the time base for the real time timer. It draws
a minimum of current (a few micro-Amps) and can therefore be backeded up by a small
lithium battery when the board is powererd down.
From the main clock oscillator, the CPU generates two further clocks by using two PLLs.
PLLA provides the processor clock (PCK) and the master clock (MCK). PLLB typically
provides the 48 MHz USB clock and is normally used only for this purpose. The clocks of
most peripherals are derived from MCK. These include EBI, USART, SPI, TWI, SSC, PIT
and TC.
Some peripherals like the programmable clocks and the timer counters (TC) can also run
on SLCK. The real time timer (RTT) always runs on SLCK.
Clock Frequency Source
PCK (Processor Clock) 528 MHz PLLA
MCK (Master Clock) 132 MHz PCK
USB Clock 480 MHz UPLL
Slow Clock 32.768 KHz Slow Clock Oscillator
Table5.3.AT91SAMA5D3x Clocks
5.9.2. Programmable Clocks
The programmable clocks can be individually programmed to derive their input from
SLCK, PLLA, PLLB and Main Clock. Each PCK has a divider of 2, 4, 8, 16, 32 or 64.
The StampA5D3x features three programmable clocks PCK0/1/2.
5.10. Power Management Controller (PMC)
5.10.1. Function
The PMC has a Peripheral Clock register which allows to individually enable or disable the
clocks of all integrated peripherals by using their "Peripheral Identifier" (see TableB.1,
“Peripheral Identifiers”). The System Clock register allows to enable or disable each of
the following clocks individually:
• Processor Clock
• DDR Clock
• LCD Clock